25 days old

Physical Design Engineer

San Jose, CA 95113
  • Job Code
Job Description

Intel Ethernet Products Group (EPG) delivers best-in-class Ethernet products and is part of the Connectivity Group which is at the heart of Intel's transformation from a PC company to a company that powers the cloud and billions of smart, connected computing-devices. EPG's compelling Ethernet products move the world's data and are the foundations of cloud service and telecommunications data centers. We are a team of problem solvers, experimenters, and innovators who are dedicated to designing the network technologies that currently lead and continue to transform datacenter ecosystems. As a world-class organization, we're looking for outstanding talent to accelerate our growth during an exciting time in Ethernet networking marketing technology. If you're ready to be a part of this journey, then we want to hear from you.

We offer, paid sabbatical, Immediate vesting at 100% of company matched 401k contributions, Annual and Quarterly Bonuses, Stock Programs, On-campus health clinics, fitness classes, spas, healthy meals, cafe options and so much more.


In this position you will be part of a world class Ethernet IP and SOC design team responsible for the design and development of the Ethernet Controllers and Networking Processing of the Network Division Silicon Engineering team. You will perform all aspects of the physical design flow from engaging with design team through synthesis, place and route, timing analysis and power reduction; This is a great opportunity to join a talented team and will include lots of product innovation on cutting edge technologies.


Responsibilities will include but not limited to:

  • Drive technical activities during all phases of physical design execution Work extensively with SoC and RTL teams to help optimize/converge the designs to achieve the best Power, Performance, and Area (PPA).
  • Logic synthesis of design blocks, Formal Equivalence Verification (FEV), Clocking network planning and analysis, Auto Place-and-Route (APR) using Synopsys ICC tools / Cadence Innovus tools, Timing signoff and timing ECO using Synopsys Prime Time, Physical verification - Layout vs. Schematic (LVS), Design Rule Checks (DRC), Electrical Rule Checks (ERC).
  • Eager to improve, influence tools, flows and overall RTL to GDS physical design methodology with data-drive approach.


Minimum Qualifications

  • Bachelor's degree in Computer Science, Electrical or Computer Engineering or in a similar field of study.
  • 6+ years of overall experience.
  • Experience in semiconductor device physics
  • Experience with Physical Design and verification Tools, Flows and Methods (such as Design Compiler, ICC2/Innovus, Primetime, etc.)

Preferred Qualifications

  • Master's degree in Computer Science, Electrical or Computer Engineering, or in a similar field of study.
  • Experience working on advanced process nodes such 7nm and below.
  • Experience in either of STA Integration PnR Flow or Physical Verification
  • Good experience with Redhawk for signal EM and IRdrop analysis.

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Other Locations

US, Arizona, Phoenix;US, Oregon, Hillsboro;US, Oregon, Portland

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-06-04 Expires: 2022-07-05

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Physical Design Engineer

San Jose, CA 95113

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