28 days old

Physical Design Engineer - STA

San Jose, CA 95113
  • Job Code
Job Description

Amazing begins here. Intel is seeking highly qualified candidates to join our Physical Design team in the Switch and Fabric Group within our Network and Edge Group. We are looking for motivated, passionate, and talented physical design engineers to build the next generation of programmable high-speed network switch ASICs. We're a strong, vibrant, cross-site team that helps drive Intel's programmable switching technology and products to position Tofino as the switching platform of choice for Cloud and Data Center network deployments.

In this role, you will be working on Static Timing Analysis (STA) flows related to constraints development, timing analysis and timing closure. Our ASICs are developed on leading edge manufacturing processes and require strong foundations in timing analysis such as latch-based timing, SI crosstalk, glitch analysis, on-chip variation, etc., to ensure accuracy, while maintaining performance, reducing turnaround times, and using compute resources efficiently. Timing constraints development and validation are other key areas, where your role will be critical to ensure the success of our chips. You will also contribute to timing closure of designs from blocks to full chip by working with team members in Logic Design, Design For Test (DFT), and Physical Design. Strong scripting skills are required to be successful in this role.

Responsibilities will include, but are not limited to:
- Defining and implementing methodology for efficient and accurate multimode, multicorner, multivoltage STA at block, subsystem, and chip levels.
- Writing and validating timing constraints for different modes for various IP in the chip.
- Performing timing rollups, analyzing timing violations, generating ECOs, and guiding team members on timing convergence.
- Composing scripts within STA tools to automate checks and custom reporting as well as scripts to automate timing execution and timing snapshot or indicator generation.
- Collaborating with team members in allied disciplines and in different geographies.


Educational Requirement:
- Bachelors degree in Electrical or Computer Engineering or related field plus 6 years of industry work experience., or
- Masters degree in Electrical or Computer Engineering or related field plus 4 years of industry work experience., or
- Ph.D. in Electrical or Computer Engineering or related field plus 2 years of industry work experience.

Minimum Required Qualifications:
- 5 years of expertise with industry leading STA and timing ECO tools such as PrimeTime, Tempus, etc., on sub-10 nm process nodes.
- 3 years of proficiency in developing timing constraints.
- 5 years of experience in Tcl and Perl/Python programming.

Additional Preferred Qualifications:
- 3 years of experience in timing analysis and closure of designs with variation-aware STA signoff criteria.
- 2 years of experience in closing timing in different modes such as scan shift, test capture at speed, etc.
- Knowledge of areas that interface with STA such as IR drop analysis, DFT, etc.
- Awareness of multi-voltage implementation.
- Experience in performing SPICE simulations to validate timing paths.
- Experience with digital implementation flow.

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Other Locations

US, Arizona, Phoenix;US, North Carolina, Raleigh

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-06-01 Expires: 2022-07-02

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Physical Design Engineer - STA

San Jose, CA 95113

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