21 days old

Platform IP Micro-Architect

San Jose, CA 95113
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Job Description

Platform IP Micro-Architect

Intel is seeking highly qualified engineers to join the CAG (Custom-Logic ASIC Engineering Group) within DCAI (Data Center and Artificial Intelligence Group) in our IP Platform Development team. We're looking for a motivated, passionate, and talented micro-architect to develop Accelerator Platform IP blocks for our next generation HW accelerators. We're a strong, vibrant, cross site team that helps drive IP product development for Cloud and Data Center applications.

In this role, as part of the IP Platform Development team, you will need to be passionate about developing high-performance IP for HW acceleration of key Cloud and Data Center workloads. You will have an excellent opportunity to define the next generation Intel IP Platform for HW acceleration. In this position you will gain valuable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.

Responsibilities will include, but are not limited to:

High level definition at the arch/uarch level to guide RTL implementation.
Specification of acceleration infrastructure blocks and their interfaces.

Aggressive pursuit of IP competitiveness against benchmarks and competing solutions related to functionality, performance, area/power efficiency and ease of use by RTL integrators.
Work will include a combination of individual contribution and leveraging team participation through technical mentoring and leadership of technical initiatives.
Being a valued advisor providing regular input into decisions by the ACC team leadership and those of broader orgs as required.

Additional Skills
The ideal candidate will have the following skills in addition to the qualifications listed below:
Must be a team player with the ability to interact effectively cross site.
Strong problem solving skills
Effective verbal and written communication skills.


Minimum Required Qualifications:
BS degree in
electrical engineering or computer engineering or related field with 13+ years relevant experience

10+ years of experience in Silicon development in RTL Design, Arch/Uarch, modeling including multiple project development life cycles with at least one as architect or lead u-architect.
4+ years of experience in PCI-Express.

Preferred Qualifications:
MSEE/MSCS or PhD or equivalent.
Strong domain knowledge in multiple of the following: AMBA AXI/APB protocol, IOSF, PCI-Express

Inside this Business Group

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, Arizona, Phoenix;US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Jobs Rated Reports for Architect

Posted: 2022-06-08 Expires: 2022-07-09

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Platform IP Micro-Architect

San Jose, CA 95113

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