16 days old

Power Delivery and Integrity Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0213125
Job Description

The Xeon Engineering Group (XEG) delivers world class Server SOCs for Intel and has a track record of being one of the premier organizations within Intel, having delivered multiple generation of Servers. We are excited for what is ahead in Intel's product leadership.

This is a position for a Power delivery and Integrity engineer. You will be part of a design team responsible for overcoming power delivery challenges through innovations and delivering solutions that span a wide range of challenges at the platform, package and SOC level.

In this role, responsibilities include although not limited to:

  • Definition of worst-case currents and voltage drop scenarios, MIM/decoupling allocation, grid choices and analysis, droop control, SOC ESD compliance, On-die droop detectors, usage of on-die delivery solutions like FIVR, LDO, and Power gates.

  • Simulations and analysis to meet voltage specifications, correlating simulation and measurement results to ensure specifications are met, Post Si characterization of worst-case workloads at the SOC level, working with HVM/EV teams and debug of any critical post-Si issues related to power integrity.


Qualifications

The candidate must have a Master's degree in Electrical Engineering or Computer Engineering and 5-7 years of experience in below listed :

  • Power delivery and integrity.

  • Metal grid optimization and analysis.

  • Solid foundation in digital/analog circuits and SOC design.

  • Domain droop specifications analysis, grid model generation and power delivery analysis.

  • Good knowledge of on-die power delivery circuits like LDOs, Power gates, voltage regulators, MIM etc.

  • Experience with Post-Si debug and techniques related to Package, Platform VR constraints, ESD, and overall SOC voltage rails specification verification.


Preferred Qualifications:
Experience in:

  • Good working knowledge of on-die power delivery techniques such as Integrated voltage regulators, LDOs, power gates and other related circuits.

  • Experience with CMOS digital circuit analysis and analog circuit design concepts is necessary.

  • Familiarity with layout design and basic layout navigation tools.

  • Knowledge of on-die power delivery networks solutions for multiple voltage domains, on-die decoupling elements, and power switching/gating schemes.

  • Familiarity with droop analysis techniques, package technologies and basic VR analysis methods, etc.

  • Good knowledge of on die metal grid, extraction, design, and analysis using industry tools like Redhawk is a plus.

  • Willing to effectively communicate and work with Architects, IP teams, Package and Platform teams to delivery solid solutions that meet specifications.

  • Familiarity with power delivery DFx circuits, ESD clamp protection schemes is a plus.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.



Other Locations

Virtual US and Canada


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$132,940.00-$199,800.00


Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.


Intel is committed to a culture of accessibility.  Intel provides accommodations to applicants and employees with disabilities.  Find information and request accommodation here

Posted: 2022-05-10 Expires: 2022-06-11

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Power Delivery and Integrity Engineer

Intel
Santa Clara, CA 95050

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