24 days old

Power Delivery Designer and Manager

Intel
Santa Clara, CA 95050
  • Job Code
    JR0224090
Job Description

The Xeon Engineering Group (XEG) delivers world class Server SOCs for Intel and has a track record of being one of the premier organizations within Intel, having delivered multiple generation of Servers. XEG has multiple products in development. We are excited for what is ahead in Intel's product leadership.

This is a position for a Power delivery and Integrity Designer and technical manager. You will be responsible for both managing the work of a design team as well as a technical contributor in charge for overcoming power delivery challenges through innovations, delivering solutions that span a wide range of challenges at the platform, package and SOC level, and work on improving power integrity during the post-Si phase of the design.

In this role, responsibilities include although not limited to:

  • All work related to SOC Pre- and Post-Si Power Delivery design and integrity, including pathfinding, design, post-Si enabling through production.

  • Contributing, enabling, and driving innovation across the Xeon SOC power delivery space.

  • Drive design methodologies and key functional areas providing technical leadership and guidance.

  • Ensure smooth cross team communications from the SOC, IP, architecture, power, platform, and packaging teams in all phases of the design.

  • Drive clear and open communication to higher level management and customers from schedules to issue resolution plans related to Xeon SOCs.

  • Influence tools and flows with data driven approach to improve generation to generation.

  • Lead, mentor and remove obstacles for engineers in the team to achieve milestone and grow both technically and professionally.


Qualifications

Minimum Qualifications:

  • The candidate must have a Bachelors degree and 8+ years of experience OR M.S. degree in Electrical or Computer Engineering and 6+ years of experience in the listed requirements.

  • Proven track record of CPU power delivery design, integrity including knowledge of platform and package constraints.

  • Proven track record of managing design teams and delivering CPU products that met schedules, performance, and market requirements.

  • This record must cover all phases of design from product concept, design through tape-in, post-Si work through production.

  • Experience with digital and analog design, validation, circuit simulation, low power techniques, power delivery and integrity methods and solutions.

  • Good knowledge of on-die power delivery circuits like LDOs, Power gates, voltage regulators, MIM, grid design and associated tools etc.

  • Experience with Post-Si debug and techniques related to Package, Platform VR constraints, and overall SOC voltage rails specification verification.


Preferred Qualifications:
Experience in:

  • Familiarity with techniques utilized for Debug of Si issues in the post-Si environment along with a good understanding of electrical validation using bench equipment is a definite plus.

  • Familiarity with tools like Redhawk for grid extraction and analysis.

  • Solid hands on experience of circuits related to power delivery.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-06-03 Expires: 2022-07-04

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Power Delivery Designer and Manager

Intel
Santa Clara, CA 95050

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