22 days old

Power Management System Architect

Intel
Hillsboro, OR 97123
  • Job Code
    JR0214771
Job Description

The Data Center Platform Architecture Integration and Validation (PAIV) team is looking for a Power Management System/debug Architect to join their dynamic and growing organization. You will bring broad understanding of multiple system areas and interfaces with Architecture, Design, and post-silicon Validation teams in improving at scale validation content and providing feedback for future at scale platform level remote debug features.

Responsibilities will include but not limited to:

  • Creating, defining, and developing the at scale system validation environment and test plans.
  • Uses and applies emulation and platform level tools and techniques to ensure performance to spec.
  • Define Power Management debug strategies and lead team with validation debug
  • Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre - Silicon Validation teams in improving Post-silicon test content and providing feedback for future on die debug features.

The candidate should exhibit the following behavioral traits:

Strong problem-solving skills.

Multitasking skills.

Strong written and verbal communication skills.

Proficient to work in a dynamic and team-oriented environment.

Good networking, communication, and influencing skills.

Excellent track record of team skills and collaboration skills.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a positive factor in identifying top candidates. Requirements listed may be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Requirements:

  • The candidate must have a Master's degree in Electrical Engineering, Computer Engineering or a related field.
  • Minimum 5+ years of experience in:
    • Platform Debug Stability and/or Mean Time Between Failure (MTBF) Validation methodologies.
    • Experience with X86 and/or systems architecture.
    • Silicon and/or platform validation.

 

Preferred qualifications:

  • Platform or Post silicon SOC validation experience
  • Experience with BIOS/Firmware and silicon debug.
  • Experience in Power Management system validation
  • Experience leading teams to validate functionalities and debug complex issues
  • Memory architecture.
  • Demonstrated experience working across functions to deliver products

Inside this Business Group

The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-05 Expires: 2022-06-05

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Power Management System Architect

Intel
Hillsboro, OR 97123

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