13 days old

Pre Si Validation Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

The world is transforming - and so is Intel! Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world.

With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver IP solutions for products that impact customers lives? If so, Come join us to do something wonderful!

In this position you will be working as part of a Pre-silicon Power Management Validation Team on current and next generation server products

Responsibilities will include although not limited to:

  • Ability to understand/co-relate the IP architecture specs to design implemented to create test plans, coverage, identify gaps in the spec documentation, debug etc for solid validation execution
  • Create holistic feature testplans, testbench environment to support scoreboards, stimulus, drivers etc for power management IP(s) validation
  • Develop/Utilize various tools and/or methodologies with the goal to ensure high quality IP delivery to customer
  • Communicate/Coordinate effectively with validation, design and architecture teams
  • Participate in the debug of customer issues, silicon sightings etc and develop new strategies to source the issues on pre-silicon models for current/next generation

You will also have:

  • Problem solving Skills even in ambiguous environment
  • Ability to Multitask
  • Strong Written and Verbal Communication Skills
  • Ability to Work in a Dynamic Team Oriented Environment


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience - OR - Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of experience in:

  • Verilog, System Verilog
  • Digital design
  • Computer architecture
  • Hands on experience in OVM/UVM methodologies
  • Strong Object oriented programming based background
  • Scripting experience in languages like Python, Perl etc

Preferred Qualifications

  • Power Management IP, Power Management SoC, DFX knowledge

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-08-04 Expires: 2022-09-04

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Pre Si Validation Engineer

Santa Clara, CA 95050

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