Hardware emulation has become an indispensable validation tool for large and complex SoCs targeting data center, networking, AI, and supercomputing applications. Our team has an opportunity for you to participate in creating and using leading edge validation technology related to emulation.

In this role, you will work with cross-functional teams - including model builders, RTL developers, Software Tools team and BIOS developers to gain a deep understanding of SoC micro-architecture and architecture in order to define emulation platform requirements and to develop and scope test plans, bring up SOCs on emulation, root cause SoC/Processor test fails and emulator environment issues. You will also be involved in executing test plans, which includes content/tool development, test failure debug, and ensuring functionality as per specifications.

Your solid design, debug, communication, and teamwork skills will be essential. Additionally, you will be responsible for inventing solutions to improve the effectiveness of the Emulation platform with respect to stimuli, debug and stress.

In this role responsibilities include, although not limited to:

• Develop Pre-Silicon functional validation tests to verify system will meet design requirements and execute tests on SOC emulation models.

• Create test plans for RTL validation.

• Find and implement corrective measures for failing RTL tests.

• Analyze and use results to modify testing.

• Understand validation requirements and work to improve validation tools/flows/methodologies.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 4+ years of experience in:

OR

Master's degree in Electrical/Computer Engineering or Computer Science and 2+ years of experience in:

• System Verilog

• Computer Architecture, Memory and IO technology

• C/C++Perl, Python and shell scripting

Preferred Qualifications:

Experience in:

• FPGA or emulation.

• Waveform debugging using Verdi. log files and microcode trace dumps.

• x86

• Debug SOC verification environment and exposure to PCIE, Memory(DDR) feature validation in SOC environment.

• Design verification, writing tests and debugging in the emulation environment.

• Experience with FW debug and bring-up is a added plus for this position.

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.