21 days old

Pre Silicon Validation Engineer/Lead

Santa Clara, CA 95050
  • Job Code
Job Description

In this position you will be working as part of a Pre-Silicon validation team on current and next generation server SoCs.
Key responsibilities include, although not limited to:
    Verification of the microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking. Fundamentals of formal verification technology, including model checking and writing formal assertions to express architectural intent of designs
    Formal verification principles and methods
In addition to the qualifications below, the ideal candidate will also demonstrate:
    Solid problem solving and debugging skills.
    Willingness to work closely with various chip design disciplines and cross site teams.
    Excellent verbal and written communication skills.
    Motivated, self-directed and work effectively both independently and in a team environment.


Minimum Qualifications:
    Candidate should possess a Bachelor's degree with 4+ years experience.
    Master's degree with 3+ years of experience in VLSI Electronics, Electrical Engineering, Computer Engineering or Computer Science.
    Expertise in Formal Property Verification
    Knowledge of Formal Abstraction Techniques. 

Preferred Qualifications:
    Experience in SoC Connectivity using Formal methods. 
    Computer Architecture, Server Architecture, Digital Logic 
    Expertise in writing System Verilog Assertions.
    Experience with any of the Formal vendor tools like JasperGold, VC-Formal or Questa PropCheck tools
    System Verilog/UVM
    Basic Scripting - Python, Perl, Shell.
    High Speed IO protocols like PCIe, CXL.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-07 Expires: 2022-06-07

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Pre Silicon Validation Engineer/Lead

Santa Clara, CA 95050

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