15 days old

Pre-Silicon Validation/Verification Architect

Folsom, CA 95630
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Job Description

We are looking for strong senior talent to work with Intel's latest cutting-edge DDR PHY IP.

As a Validation Architect, you will be responsible for defining strategy and quality for pre-silicon validation, working with the team for improvements required in the validation methodology, review and sign off of Validation Architecture Spec, Global Validation Plan, test plan, corrective and preventive action plans. The Validation Architect will be responsible for working with the overall Validation team across different phase of programs starting from TR and Early enablement of validation environment, reviews, milestone and TI sign off.

In this role you will be the focal point across organizational partnerships in Architecture, Design, MRC FW developers and Validation teams within Intel across different sites.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates

Minimum Qualifications

Candidate must have a Bachelors degree in Electrical/Computer Engineering and/or Computer Science and 9+ years experience in: - OR - a Masters degree in Electrical/Computer Engineering and/or Computer Science and 6+ years experience in: - OR - a PhD degree in Electrical/Computer Engineering and/or Computer Science and 4+ years experience in:

  • Creating verification environment for IP
  • Validating complex IPs
  • System Verilog and verification methodologies like OVM, UVM is a must have
  • Technically guiding pre-si verification team with use of functional test strategies, directed, random, stress test generation, debug flows, scenario validation
  • Working individually and as part of high performing team delivering product starting from creation of spec, verification infrastructure and execution strategy and delivering product
  • Defining new, innovative and transformational strategies to shift-left and find Hardware/Firmware bugs faster and prior to tape-in, minimizing any escapes into post-silicon

Preferred Qualifications

Experience in/with:

  • DDR interface
  • DFI interface
  • PHY IP validation

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Jobs Rated Reports for Architect

Posted: 2022-05-08 Expires: 2022-06-08

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Pre-Silicon Validation/Verification Architect

Folsom, CA 95630

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