The world is transforming - and so is Intel!  Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower peoples digital lives.

Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful!

As a Verification Engineer, you will be working on Mixed-Signal IP delivering to multiple Server SoCs.

Responsibilities will include but will not be limited to:

• Test bench development, directed/constrained random test generation in OVM/UVM

• Closely working with design team to review specifications and architecture, define verification plan & coverage, and improve methodology

• Run RTL and gate level functional verification, debug failures, and analyze coverage

• Support mixed-signal verification using Verilog models of analog IP

In addition to the qualifications listed below the ideal candidate will also have:

• Analytical and problem-solving skills

• Verbal/written communication skills

• Effective team player with continuous learning mindset

• Willingness to balance multiple tasks

• Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience

-OR-

Master's degree in Electrical/Computer Engineering or Computer Science and 2+ years of experience

-OR-

PhD in Electrical/Computer Engineering or Computer Science.

Preferred Qualifications:

• IP/SoC verification using System Verilog/ Open Verification Methodology (OVM)/Universal Verification Methodology (UVM)

• Implementation of verification environments that include use of constrained-random stimulus

• Code/Functional Coverage analysis

• Reading and interpreting technical specs and Register Transfer Level (RTL) code

• Writing System Verilog Assertions (SVA)

• Mixed-Signal Verification

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.