3 days old

Principal Engineer, Silicon Development Architect

Intel
Santa Clara, CA 95050
  • Job Code
    JR0222314
Job Description

We are seeking an experienced and dynamic Silicon Development Architect for Intel's IP Engineering Group (IPG) which is part of the Design Engineering Group. IPG's Test Chip Engineering team is chartered with transforming Intel and DEG/IPG with silicon-proven test-chips for leading-edge IPs and technologies. IPG Test Chip Architect will drive pre-Silicon Architecture development of Test Chips for PPA/Technology co-optimization, Foundational IPs, Complex IP Sub-systems in support of IP and Technology certification ahead of product intercept for internal IPG customers as well as support external customers in partnership with Intel Foundry Services (IFS). Responsibility includes close collaboration with Technology Development, IP and SoC teams to define architecture/micro-architecture and partner with design team to implement requirements for Technology co-optimization and IP validation through test-chips, IP test-chip strategy/planning and guiding design team through project milestones leading to Test Chip TI and post-Silicon bring-up of Test platforms. Test Chip Architect will report directly to the Test Chip Group General Manager in the IP Engineering Group (IPG).

The position requires strong analytical, technical and business partnering/influencing skills. The candidate must have experience in architecting complex IPs and IP Sub-systems for SoC projects in the areas of Analog/Mixed-Signal IPs, Foundational IPs as well as Soft-IPs/Controllers. The candidate must have excellent written and communications skills, and a good understanding of Intel's highly complex products, technologies, and business strategies. The position requires strong business and technical acumen, problem-solving skills, multitasking ability, and attention to quality and detail. The job is in a fast-paced environment and requires a dynamic individual to succeed. The candidate must be results-oriented, capable of synthesizing and abstracting complex information into clear messages. The position requires understanding the needs of our IP design partners and driving the test-chip architecture efficiently to address those needs with urgency and customer obsession. Working with cross-organizational stakeholders to solve engineering problems unique for our customers.

Responsibilities will include:
Leading Test Chip architecture in partnership with IP teams and Test-chip development team
Partnering with Test-Chip team leads to deliver a predictable roadmap aligned to DEG/IPG vision of delivering silicon-proven IPs
Feature architecture definition/prioritization, strategy for Hard-IP and IP Sub-system test-chips spanning silicon, FPGA prototyping, HW/FW/SW interfaces
Mentor design leads/micro-architects on career growth plans and engagement, while driving high retention levels.
Engage with DEG IP and SoC leaders to drive transformation for our Test Chip Architecture, Integration, TFM and delivery methodologies.
Partnering with IPG APAC team to develop test-chip pre-Silicon architectures


Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Minimum 15+ years of experience developing IP (HIPs, SIPs) and IP Sub-system (IO interfaces, Embedded systems) architecture for complex IP/SoC designs.
MS or Ph.D in Electrical Engineering, Computer Science or semiconductor related majors preferred
Knowledge of architecting, developing Foundational IPs and Complex Analog Mixed-Signal IPs, HSIO, Memory Sub-system and Fabrics required
Experience with complete full project development cycle, including definition, development and post-Silicon support
Deep hands-on knowledge of IP/SoC development across RTL design/integration validation and BE methods
A combination of business acumen, organization savvy, networking capabilities, and expertise to get results across multiple groups and disciplines
Strong self-initiative and persistence, ability to deal with a high degree of ambiguity and drive clarity in key areas
Detail orientation and ability to gather, analyze and interpret data to drive financial results
Strong communication and presentation skills and ability to handle high degrees of task and deadline pressure

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, California, Folsom;US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-25 Expires: 2022-06-26

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Principal Engineer, Silicon Development Architect

Intel
Santa Clara, CA 95050

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