11 days old

Process Voltage Temperature and Timing Methodology SoC Design Engineer

San Jose, CA 95113
  • Job Code
Job Description

The mission of Intels Programmable Solutions Group (PSG) is to drive the future for FPGAs and Structured ASICs technology/solutions around the globe.

With the Performance & Power Team, you'll be surrounded by some of the brightest minds/engineers in the world as we work across the Programmable Solutions Engineering team to extend our Performance per Watt leadership across all product families and variants. 

As a Process Voltage Temperature and Timing Methodology SoC Design Engineer, you will have the following responsibilities:

  • Define PVT corners for optimal PPA for all FPGA, SOC & ASIC products.

  • Define and drive design signoff methodology for standard cell, custom and analog design styles. 

  • Define and minimize design timing guard band, accounting for affects such as aging and OCV.  C

  • Collaborate with manufacturing teams to adjust guard band based on post-silicon data. 

  • Collaborate with the cross-functional teams to tackle new challenges in latest process technology nodes, for efficient design implementation and execution. 

The ideal candidate should exhibit the following behavioral traits:

  • Strong communication skills and attention to detail are essential for success in this role.


You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


  • Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field.

Minimum Qualifications:

  • 5+ years of experience in SoC design closure.

Preferred Qualifications:

  • Knowledgeable with device physics and circuit simulation.
  • Familiarity with EDA tools like DC, Primetime, Spice, etc.
  • Master's Degree in Electrical Engineering, Computer Engineering, or related field.
  • Experience with timing & power related Silicon correlation.
  • Familiarity with FPGA design tools such a Quartus or Vivado.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Posted: 2022-05-08 Expires: 2022-06-09

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Process Voltage Temperature and Timing Methodology SoC Design Engineer

San Jose, CA 95113

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