23 days old

Reliability/ ESD Verification Engineer

San Jose, CA 95113
  • Job Code
Job Description

Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person globally, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenges that come with changing the world.

Join us to develop new technology that will provide Intel a competitive advantage in Programmable Solutions Group (PSG). If you find it exciting to work in a diverse team that innovates with other Intel advanced technology groups, with other industry leaders and academia, then we have your opportunity. As a Technical lead of FPGA Full chip Global Reliability team, you will be responsible for all aspects of Reliability verification for our next generation Full chip product execution, as well as take an active role in next generation methodology development and flow enhancements.

Responsibilities include but not limited to:

  • Power distribution network design and validation
  • Provide Electro Static Discharge (ESD) and latch up planning including Single Event Latchup (SEL) and signoff
  • Perform  IREM: power grid drop, Electro Migration (EM) spec definition and verification, physical and reliability collateral generation, and database management
  • Power electrical and Design rule checking (ERC/ DRC)
  • System level power delivery analysis including power up and power down analysis
  • Proficiency in tools, flows and methodology development needed to verify and debug


Education Requirements

  • Bachelor's Electrical Engineering, Computer Science, or equivalent with 6 years of relevant experience

  • Master's in Electrical Engineering, Computer Science, or equivalent, with 4 years of relevant experience

Minimum Experience

  • ESD cell design and/or implementation and signoff

  • Experience in power distribution network design, IREM, ERC, Design Rules Check (DRC)

Preferred Qualifications

  • Verilog, Spice, full custom, and ASIC design flows with 5 years of experience

  • Analog design experience

  • Experience with PERL/Python, TCL, Linux Shells

  • Tool experience in any of the following: Redhawk, Totem, Seahawk, RapidESD, Vortex, UPF, ERC, DRC

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, Santa Clara;US, Oregon, Hillsboro;US, Texas, Austin;Virtual US and Canada

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Intel is committed to a culture of accessibility.  Intel provides accommodations to applicants and employees with disabilities.  Find information and request accommodation here

Posted: 2022-05-02 Expires: 2022-06-02

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Reliability/ ESD Verification Engineer

San Jose, CA 95113

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