1 day old

Reliability Statistical Modeling Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0221829
Job Description

You will be a key part of the Technology Development and Modeling (TDM) team, which is responsible for a range of reliability and statistical analysis solutions to internal and external partners, including:

  • Transistor degradation analysis, process variation, oxide wearout, ESD, soft-errors, and reliability verification across multiple design hierarchies and process technologies.
  • Interacting with EDA vendors to integrate Intel reliability/statistical analysis models within their EDA frameworks.
  • Working closely with multiple Intel organizations and industry partners to develop and deploy solutions that support parametric variation (process/reliability) analysis across SoC/IP designs.
  • Involvement in developing AI/ML, data analytics and associated automation to improve parametric variation analysis algorithms as well as PDK assessment.
  • About the team and organization:
  • TDM is part of Intel's Design Enablement (DE) organization. DE is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow internal and external customers to deliver winning products to the marketplace. Your work will directly enable design teams to get to the market faster with leadership products based on innovative technologies.
  • As a member of TDM you will be at the forefront of co-optimizing Intel's state-of-the-art process technology which allows customers with diverse design needs to enable best-in-class products for data-centric applications. Tech Definition and Modeling Team serves as the design interface with the process development team and works out key design/process interactions for all new Intel processes.


Qualifications

You must possess the "minimum qualifications" listed below to be considered for this position. "Preferred qualifications" are not required, but all other things being equal they will give you an advantage in the interview process.


Minimum Qualifications:
Master's degree in Electrical or Computer Engineering and at least 1 year of professional work experience OR a Ph.D. in the same fields of study. In addition, you must possess both of the following qualifications:

  • At least 1 year of programming experience in C/C++
  • At least 6 months of experience in 2 of the following areas: device physics, reliability analysis/modeling, robust circuit design and statistical analysis.

Preferred Qualifications:

  • Scripting with languages like Python, Perl, Tcl, etc.
  • Circuit simulators like HSpice or Spectre
  • Circuit-level variation analysis (variation features in simulation tools, Solido, etc.)

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.



Other Locations

US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-08-09 Expires: 2022-09-10

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Reliability Statistical Modeling Engineer

Intel
Santa Clara, CA 95050

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