Job Description
The Analog Circuit Design Engineer designs, develops, modifies and evaluates complex analog and mixed signal electronic parts, components or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems. This role is responsible for the design and development of electronic components. We are looking for the right person to take a Senior Analog Design role in the design and analysis of analog circuits - someone who will seize the opportunity to lead, design, and validate High Speed IO design IPs circuits such as DLL, TX, Rx, Voltage Regulators and References, High Voltage Circuit Design such as level shifters, charge pumps, and bias circuits, etc. Additional Responsibilities may include (but are not limited to): Design of analog mixed signal IP and chip layout Conduct circuit simulations and checking Complete device evaluation and characterization, Document specifications Complete prototype construction and checkout Modify and evaluate semiconductor devices and components Perform developmental and/or test work Review product requirements and logic diagrams Plan, organize, and design projects or phases of design projects. Respond to customer/client requests or events as they occur. Develop solutions to problems utilizing formal education and judgment.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's in Electrical/Computer Engineering, Computer Science or related field plus 10+ years of relevant experience or a Master's degree in Electrical/Computer Engineering, Computer Science or related field with 8+ years of relevant experience. experience in SOC/IP high speed IO analog/mixed signal circuit design including: In depth hands on experience in designing, testing and validating analog and/or mixed signal circuits with sub-micron CMOS technology. Strong experience in high speed IO circuit design in any of these areas: Rx, Tx, LDO, PLL, DLL, and clocking circuits. Solid understanding of deep sub-micron device physics, process technology and manufacturing. Knowledge of analog layout techniques, including floor-planning, matching, shielding and parasitic optimization. Strong background in VLSI and industry standard CAD tools for schematic capture, simulation, layout and physical verification (examples: Cadence adexl, Spectre/Ultrasim/AMS Designer /Virtuoso). Preferred Qualifications: Experience in mixed signal IP design. Good communication and leadership skillsRequirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.