24 days old

Senior Design for Reliability Engineer

Hillsboro, OR 97123
  • Job Code
Job Description

To support Intel IDM 2.0 and world leading Intel Foundry Services (IFS) strategy, Technology and Design Enablement Quality and Reliability group is looking for talents at different levels and in different areas to join this exciting journey to drive design enablement in quality and reliability domains with Ease of Use (EoU) features on Intel technology to build competitive design and IP ecosystem to meet external and internal customer needs for industry leadership. The general reliability design enablement areas include but are not limited to DTCO (Technology-Design Co-Optimization), PDK (Process Design Kits), Hard and soft IP (Intellectual Property) ecosystem, TFM (Tool/Flow/Methodology) in EDA, DFR (Design for Reliability), PPA (Power Performance Area) and Reliability co-optimization.

This senior technologist will work on advanced technology feature enablement in industry EDA (Electronic Design Automation) tools and flows with focus on quality and reliability.

This Senior Design for Reliability Engineer role will be responsible for but not limited to one or more of the following areas, multiple positions and levels will be considered based on experiences and qualifications.

  • Drive EDA tool and flow enablement for advanced technology nodes with industry EDA vendors to deliver competitive TFM with EoU features into design ecosystem, covering Si technology reliability mechanisms including FEOL (Front End of Line), BEOL (Back End of Line), ESD/LU, high voltage and other related domains.
  • Define competitive Q&R requirements, and drive closure with internal, foundry and 3rd party IP design to meet PPA and reliability spec for different market segments such as commercial, automotive, etc.
  • Drive technology reliability and design co-optimization, Ease of Use into EDA tool and ecosystem to enable IP and product decision on Intel technology for best PPA and design efficiency.
  • Pathfinding and implementation of cross domain analysis into design automation to cover emerging areas associated with technology scaling and novel product configuration, power management, thermal analysis, 3DIC, Chiplet and Chip-Package Integration.
  • Explore and Initiate machine learning (ML) and Artificial Intelligence (AI)  and novel method into early detection and migration of marginal layout for defectivity reduction and reliability coverage at early design phase and design automation tool.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must possess at least one of the 2 following degrees plus the years of experience determined for each degree in the areas specified below:

  • Master's degree in Electrical Engineering, Physics or related field with 6+ years of experience.
  • Ph.D. degree in Electrical Engineering, Physics or related field with 3+ years of experience.

Experience listed above should be in at least one of the following:

  • Reliability physics and validation methods, design for reliability for ESD (Electrostatic Discharge), LU (Latch-Up)
  • Design for Reliability for Aging including BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection), EM (Electro-Migration), High Voltage design rule, EOS (Electrical Over-Stress), etc.
  • Directing experience on reliability TFM enablement with major EDA vendors on custom and ASIC design and reliability validation tools to cover various reliability mechanisms and modeling.
  • Industry reliability method, experience for IP, and SOC (System on a Chip) design and validation in related areas.
  • Capability and hands-on experience to run standard EDA tool and flow, understand the input and output; debug and drive solutions.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Other Locations

Virtual US and Canada

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Intel is committed to a culture of accessibility.  Intel provides accommodations to applicants and employees with disabilities.  Find information and request accommodation here

Posted: 2022-05-02 Expires: 2022-06-02

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Senior Design for Reliability Engineer

Hillsboro, OR 97123

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