18 days old

Senior DFT/DFX Engineer

San Diego, CA 92101
  • Job Code
Job Description

External Manufacturing Production (EMP) team is chartered with High Volume Manufacturing (HVM) of Intel products with our 3rd party Foundry and (Outsourced Semiconductors Assembly & Test) suppliers as per Intel IDM2.0 Vision. EMP Manufacturing Quality Enhancement elite DFX (Design for Excellence) team seeks Senior/Staff DFT (Design for Test) engineers to support its operations. This is a highly strategic and visible position that present significant personal growth possibilities due to the intrinsic exposure to the entire semiconductor product development cycle from product definition to HVM.A unique opportunity of dealing with all different aspects of the most advanced and cutting-edge design, production and technology processes and interacting with the respective stakeholders within the whole company and suppliers' eco-system. Job responsibilities include: Engage with multiple SOC/IP (System On Chip / Intellectual Property (aka reusable proprietary design) design teams and BU's starting from DFX architecture definition phase and drive specific EMP DFM/DFT/DFD (External Manufacturing Production, Design for manufacturing/Test/debug) requirements. Define, Monitor and Review products DFX quality metrics (coverage, test cost, debuggability, etc.) throughout development and ramp to production. Support Yield, Test, Assembly, Packaging , Process and Foundry teams in post NPI HVM yield control and improvement. Lead non device/process integration related HVM Yield Improvement / TTR (Test Time Reduction) activities. A successful candidate must demonstrate: Experience with SOC / IP DFT control architectures like JTAG, IJTAG, IEEE1500. (Joint Test Action Group, Internal JTAG, Institute of Electrical and Electronic Engineers) Experience with ATPG patterns generation, characterization, debug and diagnosis. Experience with memory bist (Built In Self Test) patterns generation, characterization, debug and diagnosis. Team player, good inter-people relationship, and self-motivated. Basic understanding of digital fault modeling (Stuck-At, Transition, Delay, Cell-Aware) and coverage concepts. Basic understanding of SOC / IP integration, clock , power topologies and architectures. Basic understanding of Implementation and Timing Closure concepts including margins, IRdrop (Voltage Drop),


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum qualifications:
Bachelor of Science Degree or higher in EE, CS, EE or similar degree

4+ years of engineering experience

4+ years of SOC and / or DFT experience

Preferred Experience:

  • Masters of Science degree or higher in CS, EE or similar STEM degree

Inside this Business Group

Intel's Sales and Marketing (SMG) organization works with global customers and partners to solve critical business problems with Intel based technology solutions. SMG works across business units to amplify the customer voice and deliver solutions that accelerate their business. We work across numerous industries, including retail, enterprise and government, cloud services and healthcare as examples. The operations team focuses on forecasting, driving alignment with factory production and delivering efficiency tools and our marketing capability drives demand and localized marketing in locations around the globe. Our sales force navigates a complex partner and customer ecosystem while shaping product roadmaps, driving value for our customers, and collaborating to harness emerging technology trends to deliver comprehensive solutions.

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara;US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-07-30 Expires: 2022-08-30

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Senior DFT/DFX Engineer

San Diego, CA 92101

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