11 days old

Senior Director of EDA Engagement for Design Enablement

Intel
Santa Clara, CA 95050
  • Job Code
    JR0218252
Job Description

About the Group:
The Technology Development Group is responsible for the research, development, and deployment of next-generation silicon and packing technologies that will enable future Intel and Foundry customer products. The Design Enablement organization is a global team which supports both technology and product development (internal and external). This includes design innovations driven through Design-Technology Co-Optimization (DTCO) to enable the technology to deliver the best Power, Performance, Area, and Cost (PPAC) for new products; the development of test vehicles that supports the technology development process and enables the development and prototyping of design IP; and the development of Process Design Kits (PDKs), the CAD representation of the technology used by designers, which are high quality and easy to use for fast time-to-market for our products. This organization is an integral part of Intel's new IDM2.0 strategy, enabling both internal and external customers on cutting-edge technologies.

About the Role:
In this role, you will direct the strategic Design Enablement technical engagements with EDA (Electronic Design Automation) suppliers. Key activities will include:

  • Developing and driving a coherent Design Enablement EDA strategy to meet the needs of Process Design Kits and Design-Technology Co-optimization on next-generation process technology nodes.
  • Serving as the central Design Enablement contact for both tactical and strategic EDA issues that require escalated attention from an EDA supplier.
  • Planning and chairing regular executive review meetings between Intel Design Enablement and individual EDA suppliers. Identify agendas and concise key messages to achieve Design Enablement strategic directions through executive decisions.
  • Track the performance of EDA suppliers to their commitments through rigorous indicators.
  • Manage a small team of technical contributors to assist in the tracking of EDA related issues and indicators.

Required Skills/Experience:

  • EDA design/development experience-familiarity with the fundamental concepts associated with parasitic extraction, physical verification, auto place and route, circuit simulation, and reliability verification.
  • 5+ years of experience technically contributing or leading in a design enablement area including: test-chip development; foundational IP creation; PDK development; process modeling; semi-conductor design
  • Superb written and oral communication skills demonstrated through work experience including organizational leadership or program management.
  • Demonstrated ability to track and plan work in a disciplined fashion.
  • Demonstrated ability to set a strategic direction for a technical organization.


Qualifications

  • Masters or PhD degree in Electrical Engineering or Computer Engineering
  • 10+ years of experience working with EDA tools and/or EDA suppliers in the context of semi-conductor design, EDA design automation activities and EDA development.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.



Other Locations

US, Arizona, Phoenix;US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-13 Expires: 2022-06-13

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Senior Director of EDA Engagement for Design Enablement

Intel
Santa Clara, CA 95050

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