22 days old

Senior IP Security Logic Design Engineer

Intel
Folsom, CA 95630
  • Job Code
    JR0221969
Job Description

The Security Engineering and Architecture (SAE) team is looking for current and future digital logic design technical leaders and experts with experience in and/or exposure to pre/post-silicon validation + knowledge of scalable IP design. This role will be responsible for design of new IP roadmap features and develop secure design practices as part of Foundational Security Team's (FST) HW IP developing HW security for - several groups market segments across Intel. As a senior member of the team, you are responsible for: Driving a scalable IP development while also making the Design Integration and SOC delivery a fully automated solution. Implementing the clocking / reset strategies, and building sub-systems using various strategy/tools/methods. Check the design for Lint, synthesizability, DFX, Analyze Clock crossing, Power, Performance implications for FST HW security IP. Work closely w/ the Architect/Uarchitecture and Validation teams in determining the proper implementation strategy for new design, define and provide feedback on specifications. Develop White Box Coverage plans, understand high level IP end-to-end flows. Review design codes for efficiency/coverage and drive any paradigm shifts needed in correct-by-construction design implementation. Engage with early prototyping (w/ FPGA, Emulation teams).Actively engaged in risk analysis and validation recommendation for product Tapeouts etc. Mentoring junior members of the team and improving the overall technical bench strength of the organization. Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical leadership skills. Passion for design/ tools and methodology and strong influencing skills. Must have orientation for Quality and Commit and Deliver and Drive Innovation/efficiencies. Have strategic thinking skills to come up w/ paradigm shift solutions to critical design/validation challenges.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qulaifications:
Bachelors' Degree in Electrical Engineering or Computer Engineering or similar degree and at least 4 years experience; or Master's Degree in Electrical Engineering or Computer Engineering or similar degree and at least 3 years experience in the following:

Relevant logic design position and must have gone through multiple project cycles to gather in-depth experience

  • Digital logic design with various tools and methodologies including: System Verilog, Perl, VCS/Synopsys simulators, Lint, Synthesis, Clock Domain Crossing tools, DFX Scan and Power.

  • Sub-system/ IP design and or verification

  • PC Architecture


Preferred Requirements:

  • Knowledge of critical PC IO subsystems (e.g PCIe) and security algorithms (Crypto Engines) are highly recommended.

  • Knowledge of IO Controllers and Design and experience with standard buses / bridges such as AHB / OCP / AXI are preferred.

  • Knowledge of Low power / High Performance Designs and Practices are preferred.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.



Other Locations

US, California, Santa Clara;US, Texas, Austin


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-05 Expires: 2022-06-05

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Senior IP Security Logic Design Engineer

Intel
Folsom, CA 95630

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