29 days old

Senior Physical Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0219184
Job Description

WCS Group Intel Wireless Communication Solutions (WCS) is a world-class leader in wireless connectivity and the industry's number one provider of PC Wi-Fi/BT solutions.WCS powers ultra-fast, low latency, low power, and ultra-reliable wireless connectivity for hundreds of millions of people worldwide, enhancing experiences that range from businesses, education, and health to gaming and industrial services.What will you do?The Silicon division of the Wireless Connectivity Group is looking for a Physical Design Engineer. As part of your role:You will be part of a world-class design team responsible for designing sophisticated wireless SoCs with demanding requirements in power, performance, cost, and area.You will be part of a team responsible for the Backend stages of VLSI development, including Floorplan, CTS, routing, STA, and all Signoff activitiesIn this role you must have the following:Strong verbal and written communication skills.Ability to work well both autonomously and in an intensive, cooperative team environment.Strong comprehension of electrical behavior of materials and insight into ways to improve reliability and manufacturability.Motivation and drive to continually push improved design, productivity, and efficiency.Enjoy debugging, and problem solving in a team environment.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Bachelors Degree in Electrical Engineering or any STEM related degree with 6+ years of industry experience or

Masters Degree Electrical Engineering or any STEM related degree with 4+ years of industry experience

4+ years of SoC silicon physical design experiences on following areas:

Place and Route tools, Synopsys Fusion Compiler or ICC2 and Cadence First Encounter are preferred.
RTL-to-GDS methodologies and implementation.
Validating and fixing LVS, DRC and RV violations.
VLSI Design Automation.

Preferred Qualifications
5+ years of experience in wireless SoC or RF silicon physical designs
5+ years of experience in design partitioning, UPF, scan reordering, placement and routing, timing closure, signal integrity for full chip implementations.
3+ years of experience with Perl, Python, and shell scripts is a plus.
3+ years of experience with electrical behavior of materials and insight into ways to improve reliability and manufacturability.

Inside this Business Group

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to continue to advance PC experiences to deliver the real-world performance people demand. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.



Other Locations

US, Arizona, Phoenix;US, California, San Diego


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-06-03 Expires: 2022-07-04

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Senior Physical Design Engineer

Intel
Santa Clara, CA 95050

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