Job Description
Join us in the Xeon Engineering Group (XEG) delivering on next generation Xeon product IPs for Server markets. We are looking for a Senior Pre Silicon Verification Engineer who is passionate and willing to learn individuals to contribute on the Register Transfer Level (RTL) Design and Verification team. Your responsibilities will include but not be limited to: Lead the Pre-Si validation in various functional areas of a SOC or IP Define Pre-Si validation plans, leveraging various validation platforms including but not limited to Simulation and FPGA Develop test bench infrastructure and verification content Coordinate with other team members to align on expectations and dependencies for deliverables Collaborate with design and architecture teams to align on feature scoping, staging of feature development, and validation coverage

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 6+ years of experience -OR- a Master's degree in Electrical/Computer Engineering or Computer Science and 4+ years of experience RTL Design validation experience developing unit or system level test-benches and test plan creation. Coordinating and steering the efforts of multiple teams and team members. Developing test-bench components such as monitors, scoreboard/checkers, and bus functional models (BFMs). Experience with System Verilog Assertions and Functional Coverage. HDL such as Verilog/OVM (and/or UVM)/System Verilog. Scripting languages such as Perl/Python.Preferred qualifications: Experience with working IP and SoC Verification teams and developing solutions spanning both requirements. Experience with Security validation Experience with Embedded Software/Firmware (C/C++) Familiarity with hardware design flows (EDA) and tools: CDC, Lint, Synthesis, Logic Equivalence Checking, Timing Experience with developing FPGA and Emulation-based validation platforms Developing/validating CPU flows such as Reset, Power Management, and Boot flows.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role is available as fully home-based and generally would require you to attend Intel sites only occasionally based on business need.