10 days old

Senior Signal Integrity Engineer

Hillsboro, OR 97123
  • Job Code
Job Description

We are the Enterprise Platform Signal Integrity Group within DPEA (Data Platform Engineering and Architecture Group). We are responsible for developing the platform interconnect design guidelines for state-of-the-art server platforms, which support the latest Intel Xeon processors and other server products.  In this position you will be working with a team of Signal Integrity Engineers. You will develop interconnect/interface solutions. Your scope of responsibilities will include, but are not limited to: Working in lab to perform measurement, and correlating measurements to simulations.  Engaging with silicon designers, platform designers, package designers, electrical validation teams, external customer support teams.  Performing modeling and simulation of high-speed IO interconnects/channel.  Developing package and platform design guidelines;  Defining and evaluating circuit design features required to support interconnect performance requirements.  Creating signal measurement test plans and reviewing of measurement results.  Supporting signal integrity tool and methodology development.



You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Relevant experience can be obtained through schoolwork, classes and project work, internships, military training, and/or work experience.  

Bachelor's degree in Electrical Engineering or related field with 7+ years of total experience inclusive of the experiences below (PhD with 2+ years of applicable experience or a Master's Degree with 5+ years of applicable experience will also be considered)

Lab experience such as using lab equipment like oscilloscopes, Jbert/BertScope, TDR, VNA, or performing lab data correlation etc.
Signal Integrity design experience supporting high speed differentials signals and/or memory interfaces (e.g. PCIe, Ethernet, DDR)
Experience with EDA Tools (Mentor Graphics, Cadence, etc.)
Experience with simulation tools Matlab, HSpice, and ADS
Experience with computing and/or communications systems (hardware or software) (e.g. networking, telecommunications, server, desktop, cloud, etc.)

Preferred Qualifications

Experience with 2D and 3D field solver tools, such as HFSS or CST, etc.
Experience with silicon device modeling methods, such as IBIS-AMI or Verilog-A
Experience in design of package, connector, cable, socket, etc.
Experience in memory technology.
Experience using scripting languages (e.g. Python, PERL)
Knowledge with transmission line theory and electromagnetic field concepts

Inside this Business Group

The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-12 Expires: 2022-06-12

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Senior Signal Integrity Engineer

Hillsboro, OR 97123

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