3 days old

Senior Staff ASIC/FPGA IP Solutions Engineer

San Jose, CA 95113
  • Job Code
Job Description

The Custom Structured ASIC Engineering Group within Intel Programmable Solutions Group is seeking exceptional talent for an experienced Structured-ASIC/FPGA IP Solutions Engineer to work with a diverse team designing Intel's next generation Custom Structured ASIC (Intel eASIC) based SOCs and Customer Design solutions - someone who is passionate to improve the way we solve complex problems through teamwork or direct contributions.

In this position, the candidate would play a critical role in IP solutions for customer designs encompassing the architecture, best-in-class IP sourcing, logic design, verification and implementation of Subsystems of Custom Structured-ASIC SoCs within the Programmable Solutions Group (PSG). The candidate is expected to actively collaborate across in-house IP-engineering teams and best-in-class 3rd Party IP vendors and drive IP-solutions execution for different designs. The candidate would work closely with developers across IP Design, Verification, and Implementation engineers to ensure we develop IP and subsystems that meet our customers' needs.

Candidate responsibilities include the following:

  • Design, verification and Implementation of IPs and subsystems on Structured-ASIC (eASIC) fabric comprehending RTL coding, Integration of IPs, Synthesis, Simulation, Compilation, Timing Analysis, Power Analysis.

  • Create reference IP and subsystem designs for eASIC implementation.

  • Perform Subsystem Qualification for customized IP configurations for different designs.

  • Perform design evaluations and recommend strategies to optimize designs for important design opportunities.

  • Develop technical collateral and presentations for internal and external stakeholders.


Minimum Qualifications:

  • Bachelor or Master's degree in Electrical/Computer Engineering, Computer Science or related field with 10+ years of industry experience in SOC/IP Design and Development.

Preferred Qualifications:

  • Design and implementation experience in IPs such as PCIe, CXL, Wireless, Ethernet protocols would be desired.

  • Solid understanding of hardware design, design verification, timing analysis, clock domain crossing, and lint.

  • ASIC or FPGA design experience including Verilog/VHDL/System Verilog coding, Standard EDA flows and Synthesis tools(Design Compiler), Simulation (ModelSim/VCS/Incisive), timing closure (Primetime), Power analysis, design optimization and on-chip debugging.

  • Solid Tcl, Perl and/or Python scripting skills.

  • Verbal and written communication skills.

  • Independence and proven willingness to set and meet own goals.

  • Direct experience with integrating IPs and cross-functioning with IP teams.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-23 Expires: 2022-06-23

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

Senior Staff ASIC/FPGA IP Solutions Engineer

San Jose, CA 95113

Join us to start saving your Favorite Jobs!

Sign In Create Account
Powered ByCareerCast