18 days old

SERDES Applications Architect

San Jose, CA 95113
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Job Description

Intel is at the intersection of several technology inflections - artificial intelligence, 5G network transformation, and the rise of the intelligent edge - that together will shape the future of technology. We are a global leader, creating world-changing technology that enables progress and enriches lives.

As a member of Intel's Programmable Solutions Group, you will use your knowledge of high-speed IO/SERDES technology, AIB and DDR to lead efforts for building state of the art SOC and enabling customers, both internal and external, to use the Structured ASIC technology. If you are a self-driven with deep knowledge in design, verification, and communication interfaces, coupled with good communication skills, this will be a great fit for you. This is a structured ASIC team under Intel's PSG is targeting 5G, cloud computing and high-end consumer application space.


Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC.


Responsibilities include but not limited:

  • Provide leadership to customer programs with SERDES arch and other IO interface IP procurement.

  • Develop collaterals such as Handbook, Datasheet, and Application notes.

  • Support IP teams and customers to utilize SERDES for applications, protocols, architectures, and other requirements.

  • Gather requirements for next generation SERDES and specify PCS and PMA blocks of the transceiver and demonstrating technology capability.

  • Support methodology for high-speed serial IO measurements and leading the characterization team.


Education Requirement:

  • BS in Electrical Engineering, Electrical Electronics or Computer Engineering with 9+ years of experience or

  • MS in Electrical Engineering, Electrical Electronics or Computer Engineering with 7 plus years of experience or

  • PhD with 4+ years of experience.

Minimum Qualifications:

  • Experience with SERDES and protocols, such as PCI Express, or 10GBASE-KR/SR/MR/ER/LR, 25GBASE-KR, or JESD 204X, or CPRI/OBSAI, or DisplayPort or HDMI or VbyOne.

  • Experience in programming and data analysis with either Python, Matlab, Perl, C++ or any Object-Oriented language.

  • Experience with experience in SI Concepts, including sources and causes of noise and jitter.

  • Experience with experience in communication systems theory relating to SERDES, SERDES IP architecture and implementation.

Preferred Qualifications

  • Experience with DDR and AIB.

  • Experience with testing equipment, such as high-speed oscilloscopes, BERTs and VNA.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

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Posted: 2022-05-05 Expires: 2022-06-05

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SERDES Applications Architect

San Jose, CA 95113

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