4 days old

Silicon Validation Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0205579
Job Description

Come join a creative team of engineers dedicated to designing the hardware technologies that network the leading cloud-service datacenters. We are the Switch and Fabric Group, XFG, inside Intel's Network and Edge group. We are looking for a motivated and astute individual to join our team as a Lead Emulation Engineer. You will be joining a collaborative team responsible for building the world's leading programmable Ethernet switches.
Our organization works on all levels of ASIC development, starting from high-level architecture to low-level circuit design and high-volume manufacturing. Our emulation engineers are responsible for building efficient and effective directed and constrained-random emulation environments that exercise designs through their corner-cases and demonstrate conformance to specifications.
They are also responsible for bringing up driver software in emulator. They use their analytic and waveform analysis skills, strong knowledge of digital design, understanding of object-oriented programming, and detailed understanding of IEEE and IETF specifications to verify large networking ASICs comprised of tens of billions of transistors.
You will be responsible for development of emulator environments, developing test plans, coverage plans and test-plan execution.


The ideal candidate should exhibit the following behavioral traits:

  • Detail oriented problem solving and communication skills.

  • Work independently and at various levels of abstraction.

  • Thoughtful and perceptive analytical ability.

  • A genuine curiosity for understanding the system.

  • Dedicated, committed to creative problem solving and assuming responsibility.


Qualifications

Minimum Qualifications:
BS, MS, PhD Degree in Electrical Engineering, Computer Engineering, Computer Science or related degree

- 5 + years of practical experience in post silicon validation of SoC/Network - Switches/Processors and the following:

- 3+ years experience in the following:

  • c/c++ or python or Tcl

  • Test creation and debugging

Preferred Qualifications :

- Experience with  PCIE protocol

- Physical and protocol knowledge of high speed Serdes interfaces

- Knowledge of protocol analyzers is a plus

- Experience with emulation is a plus

- Experience with Board/Platform-level debug , silicon failure analysis , PVT and power measurement is a plus

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Posted: 2022-05-15 Expires: 2022-06-15

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Silicon Validation Engineer

Intel
San Jose, CA 95113

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