27 days old

SMTS Applications Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0220444
Job Description

Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person globally, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenges that come with changing the world.

We are a global leader, creating world-changing technology that enables progress and enriches lives. Intel is at the intersection of several technology inflections - artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology. As a member of Intel's Programmable Solutions Group, in this role the candidate will use knowledge of Post-Si validation, SERDES, and Signal integrity and power integrity to validation or new and next generation SOC products.

 

A successful incumbent will interface with other teams related to board design and packaging to lead efforts at a system level in enabling customers, both internal and external, to use the Structured ASIC technology. The candidate should also be familiar with lab measurements and debug. Structured ASIC team: This is a structured ASIC team under Intel's PSG is targeting 5G, cloud computing and high-end consumer application space. Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC.

 

Responsibilities include but not limited:

  • Drive post-silicon debug to root cause and provide resolution.

  • Work on improving validation infrastructure including: equipment, automation, scripting, fixtures and lab-setup.

  • Lead effective cross-functional efforts for process improvements, technical initiatives and resolutions.

  • Define methodology for high speed serial IO measurements.

  • Validate PCS and PMA blocks of the transceiver.

  • Provide characterization and evaluation boards.

  • Train and provide engineering support to Intel's worldwide customers and applications team.

  • Work in the lab to confirm some of the simulation findings.

  • Perform protocol specific characterization and author characterization reports.

  • Work with IP teams and customers to ensure proper usage of the SERDES for various applications and protocols.

 


 


Qualifications

Minimum Education Requirements

  • Bachelors' degree in Electrical Engineering, Electrical Electronics or Computer Engineering

  • Masters' degree in Electrical Engineering, Electrical Electronics or Computer Engineering

Minimum Qualifications

Must have 7+ years experience in the following:

  • Power-on, system and functional level testing.

  • Experience in SOC architecture including ARM processors.

  • 25GBASE-KR or JESD204x or CPRI/OBSAI or DisplayPort or HDMI or VbyOne 10GBASE-KR/SR/MR/ER/LR,SERDES and protocols such as PCI-Express or

  • Communications System Theory as it pertains to SERDES specifically, including PLLs and Timing Recovery (CDR).

  • Experience with test equipment such as high speed oscilloscopes, BERTs and VNA.

  • Experience in SERDES applications/characterization.


Preferred Qualifications

  • Experience in SI Concepts, including sources and causes of noise and jitter.

  • Experience transmission line theory, electro magnetics, layout - both packaging and PCB.

  • Design aspects, implementation and applications of high speed SERDES, 54G+ including PAM4.

  • Test/Automation experience.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, California, Folsom;US, California, Santa Clara


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-04-28 Expires: 2022-05-29

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SMTS Applications Engineer

Intel
San Jose, CA 95113

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