Join Intel-and build a better tomorrow. At Intel you can help build computing technology to connect and enrich the lives of every person on Earth.

You'll be part of Advanced Design (AD) within Design Enablement organization (DE).

The team works in close collaboration with various partners in process technology and design teams spanning CPU, Graphics, Networking, and Servers. The primary focus of the team is to accurately predict the impact of process changes on power, performance and area (PPA) scaling metrics thereby facilitating quick data-based decisions for PPA commits going from one tech node to the next.

As a candidate you should like:

• Physical design
• Problem-solving
• Exploring new technologies for design optimization (including but not limited to AI/ML)

About the role:

Perform all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create an optimal design. You will be working as part of a team supporting RTL synthesis and place and route experiments using internal and external vendor tools to improve Intel's product Power, Performance, and Area, for existing and future process nodes on internal Intel Architecture (IA/X86) and external ARM IP's. You will be specifically expected to deal with changes in floorplan, corresponding scaling, and its impact to power, congestion, and timing for the present technology node and predict how it would impact the scaling of power, routing and timing for the next technology node. Help improve cell utilization and transistor density metrics by leveraging leading edge tools and methodologies. You should be able to: analyze power (dynamic and leakage), performance (setup and hold), improve critical path timing, find ways to reduce congestion by making best use of available metal layers, debug tools and more.

Qualifications

Minimum Education level:

• Master's degree in Electrical Engineering or related field with 2+ year of industry work experience

Or

• PhD in Electrical Engineering or related field

Experience in the following areas:

• At least one of the following: Python, Perl, TCL, Shell scripting
• Use of industry standard placement and routing CAD tools
• SoC Physical Design
• Static timing analysis (STA)

 Preferred Qualifications:

• Floor planning and power grid setup, clock methodologies, IR droop and SI mitigation strategies, power and timing signoff conditions, and leveraging the industry standard tools, flows, and methodology to get the correct PPA tradeoffs.
• Experience performing feasibility or technology pathfinding
• Background in Artificial Intelligence and Machine Learning (AI-ML)

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Other Locations

US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.