As part of Design Enablement's Library and Technology team you will join a highly motivated group of top-notch engineers solving challenging technical problems in physical design pathfinding.

Your responsibilities will require you to participate in one or more of the following:

• Perform block PPA with emphasis on synthesis, place, and route on latest internal/external core/graphics/soc designs and target for ambitious power, performance, and area
• Work with process team to co-define next generation technology node from ground up and push Moore's law to next level
• Explore standard-cell architectures together with library team and provide guidance to library optimization and choice through block PPA
• Explore memory options for next technology nodes and provide block PPA impact
• Co-optimize TFM with EDA tool vendors (primarily Synopsys and Cadence) to boost block PPA and deliver world-class process offering
• Develop in-house physical design machine learning capability to explore design solution space and push block PPA as well as provide guidance to process technology optimization direction
• Work intensively with product teams to provide block PPA guidance as well as TFM recommendations
• Design delivery: Bring designs from block PPA and realize in silicon through test-chip and demonstrate world leading silicon

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.

Minimum Qualifications:
Master's degree in Electrical Engineering, Computer Engineering or related discipline with 2 or more years of professional experience in the areas listed below, OR a Ph.D. in the same disciplines with 6+ months of academic/research/professional work in the areas listed below.

Experience must be in the following:

• SoC/IP physical design using a Cadence and Synopsys design flow.
• Static timing analysis and physical design closure.

Preferred Qualifications:

• Power grid design and IR analysis
• Timing budgets and analysis
• IP block Power, Performance and Area analysis (PPA)
• EDA algorithm customization and optimization
• Scripting language like Python, Perl or TCL
• Artificial Intelligence and Machine Learning (AI/ML)

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.