Responsibilities include:

• Implementation of Design-for-Test capabilities on state-of-the-art silicon designs.

• Working with both external Tier-1 customers and internal product design teams during their silicon design cycle as they develop System-on-a-Chip (SoC) solutions utilizing CMOS cell-based ASIC technologies, along with integrated high-performance SerDes functions, embedded microprocessors, and high speed memory interface IP.

• Will be responsible for the development of the SoC Test Implementation plan describing the strategies to address the DFT requirements for the design, planning of the hierarchical test architecture, insertion of DFT structures, generation, simulation, and validation of test patterns for both DFT logic verification and for HVM ATE testing of the design, supporting the Static Timing Analysis (STA) team for the timing closure for the DFT modes of the design, and for supporting the Test Engineering team during silicon bring-up and New Product Introduction (NPI).

• Will also work closely with internal Test Methodology team and IP development teams.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
The candidate must possess a Bachelors 8+ years of experience OR MS in Electrical or Computer Engineering 6+ years of experience in:

• SoC Design-For-Test (DFT) principles including SCAN for logic testing, BIST and repair for memory test, JTAG Boundary SCAN.

• DFT architecture development and planning for an SoC.

• Test insertion, test pattern generation, simulation, and validation.

• Industry-standard DFT tools such as Mentor Graphics FastSCAN, TestKompress, Synopsys DFT Compiler, DFTMax, TetraMax.

• Static Timing Analysis, Synopsys PrimeTime, constraints and timing path debug.

• Scripting Languages, e.g., PERL, Tcl/Tk.

Preferred Qualifications:

• Knowledge of manufacturing tester capabilities, Automatic Test Equipment (ATE), and test program experience.

• Knowledge of DFT integration of IP (e.g. DDR, SerDes, PLL's) into an SoC.

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

US, Texas, Austin

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Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.