The Design-for-Test (DFT) Implementation Engineer is a challenging and cutting-edge position working as part of a team to implement Design-for-Test capabilities on state-of-the-art silicon designs.

You will be working with both external tier-1 customers and internal product design teams during their ASIC design cycle as they develop System-on-a-Chip (SoC) solutions utilizing CMOS cell-based ASIC technologies, along with integrated high-performance SerDes functions, embedded microprocessors, and high speed memory interface IP.

You will be responsible for the development of the SoC Test Implementation plan describing the strategies to address the DFT requirements for the design, planning of the hierarchical test architecture, insertion of DFT structures, generation, simulation, and validation of test patterns for both DFT logic verification and for HVM ATE testing of the design, supporting the Static Timing Analysis (STA) team for the timing closure for the DFT modes of the design, and for supporting the Test Engineering team during silicon bring-up and New Product Introduction (NPI).

You will also work closely with internal Test Methodology team and IP development teams.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Bachelors in Electrical/Computer Engineering and 6+ years of experience OR MS in Electrical/Computer Engineering or related field with 4+ years of experience.

4+ years of experience in one or more of the below:

• SoC Design-For-Test (DFT) principles including SCAN for logic testing, BIST and repair for memory test, JTAG Boundary SCAN.

• DFT architecture development and planning for an SoC.

• Test insertion, test pattern generation, simulation, and validation.

• Industry-standard DFT tools such as Mentor Graphics Tessent, Synopsys DFT Compiler, DFTMax, TetraMax.

• Static Timing Analysis, Synopsys PrimeTime, constraints and timing path debug.

• Scripting Languages, e.g., PERL, TCL/Tk, Python.

Preferred Qualifications:

• Knowledge of manufacturing tester capabilities, Automatic Test Equipment (ATE), and test program experience.

• Knowledge of DFT integration of IP (e.g. DDR, SerDes, PLL's) into an SoC.

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$132,940.00-$199,800.00