22 days old

SOC Design Engineer

Folsom, CA 95630
  • Job Code
Job Description

Our High Speed IO group is looking for a dynamic Design Engineer working on next gen DDR designs.

Your responsibilities in this position will include, but are not limited to:

  • Performs logic design Register Transfer Level RTL coding and simulation of the functional blocks and subsystems for inclusion in full chip designs.

  • Participates in the development of Architecture and Microarchitecture specifications for the Logic components.

  • Provides IP integration support to SoC customers and represents RTL team

  • Work with the Analog team to ensure the BMODs represent the Analog behavior accurately and work with Validation team to come up with the extensive Test plan


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must have a Bachelors degree in Electrical/Computer Engineering and 9+ years of experience - OR - a Masters degree in Electrical/Computer Engineering and 6+ years of experience in/with:

  • Reading and interpreting technical specs to come up with Microarchitecture and implement RTL design in System Verilog

  • Computer system architecture and Digital Design

  • Experience working with Multi Voltage and Power managed Designs and UPF

  • Extensive Analog Knowledge, BMOD development and Tool Flow methodologies including CDC, OSXML, VCLP etc;

  • Understand OVM/UVM methodology to interact with the Validation designers for Val content development.

  • DFX knowledge

Preferred Qualifications:

  • Domain knowledge in DDR and High speed Serial interfaces

  • Basic scan

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara;US, Texas, Austin

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-03 Expires: 2022-06-03

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SOC Design Engineer

Folsom, CA 95630

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