As part of the IP Engineering Group, the Product Library team is looking for experience standard cell library design engineer in the area of design, development, automation and delivery of standard cell and register file using Intel latest process technology for use by Intel CPU, Atom, Graphics, mixed signal IPs, Client, Sever, Chipset projects and IFS Foundry customers.

The successful candidate will be part of the production library team responsible for standard cells circuit design and optimization, physical design, design rules, reliability and optimization, understanding of standard cell physical collaterals using leading process technology for use by Intel's product design teams and Foundry customers.

Responsibilities include, but are not limited to:

• Understand Intel process design rules and library architecture specification.

• Drive layout design and optimization techniques with Cadence Virtuosos, Synopsys Custom Compiler.

• Define architecture rules checker specification for efficient layout design, optimized for area, reliability, power and performance tradeoffs.

• Evaluate impact and assessment of new design rules, drive automation of fix strategies, working with global mask design team.

• Write layout automation script, checkers for quick analysis and design rules manipulations.

• Layout pattern analysis, drive yield aware layout design and quality.

• Own generation, validation and delivery of NDM and LEF flows and std cells based collaterals.

• Acquire skill in internal automated layout synthesis tool configuration and execution, debug interface issue and align on signoff spec.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must have a bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience.

OR

Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of experience.

• Experience in digital circuit design, including CMOS combinatorial logic and sequential element design and layout.

• Experience in programming language with proficiency in one or more of the following languages: Tcl, Perl, Python, Unix Shell Scripting.

• Excellent collaboration skills across geographically distributed teams and being willing to handle ambiguity while developing expertise in new areas and delivering excellent, quantifiable results will be key to the success in this role.

• The successful candidate must possess excellent written and verbal communication skills, solid customer/result orientation and the willingness to work with external, internal partners and with EDA vendors in a flexible manner.

• Solid programming and automation skills with years of experience in one or more areas of VLSI Design Automation (Physical Design Automation, Simulation, Timing Analysis, Reliability Analysis).

Additional/Desired Qualifications in one or more areas:

• Extensive experience working with EDA vendors to drive new features and capabilities.

• Experience in the development of design automation tools/flows.

• Solid knowledge of industry-standard EDA tools for VLSI circuit and layout design.

• Experience working in the Linux environment and its development tools.

• Good engineering acumen and analytical skills.

• Quick learner with debugging skills.

• Customer oriented and willing to work in a dynamic environment.

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.