Full chip integration team is an integral part of Silicon and Systems prototyping Lab (SSPL) enabling integration and tape out of prototypes. Your work will directly enable stake holders in providing ease of use design methodologies, executing to cutting edge technologies. As part of Full chip integration team you will join highly motivated team of talented engineers works to aggressive schedules by clearly communicating technical tradeoffs, solving challenging technical problems in backend design and integration, design collateral releases and ensuring successful test chip tapeouts.

As a SOC Design Engineer your responsibilities include, but are not limited to:

• • Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs
  • Execute block-level synthesis, floor planning, clock tree synthesis, place and route, timing closure and layout cleanup.
  • Drive the block level's timing, Design Rule Checks (DRC), Layout Versus Schematic (LVS), Formal Equivalence Verification (FEV) convergence as well as participate in full chip convergence.
  • Work alongside circuit designers to debug timing constraints and debug circuit implementation issues.
  • Apply design methodologies to help execute projects effectively with high quality. Work with external customers on tapeouts.
  • Work with external customers to help SoC tape-in signoff
  • Develop design implementation methodologies, design flow automation and improvements on existing flows for increased efficiency.

Behavioral Traits:

• Strong problem-solving skills.
• Effective verbal and written communication skills.
• Ownership, communication, and influencing skills.

Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences

Minimum Qualifications:
The Candidate must possess a Master's degree in Electrical Engineering, Computer Engineering or Electrical and Computer Engineering or similar field of study.

4+ Years of experience in below areas:

• DRC/LVS Runset and algorithm development. Specific experience with Auto place and route algorithms
• C/C++/Java/Perl programming language.
• Data Structures, Algorithms and Optimizations.
• Microprocessor floor planning, FUB integration, layout design rules and schematic/layout comparison debug and correction.
• Physical layout, verification and be proficient in layout assignments from upper level layout, floor planning and component level layout.
• Physical Design Verification methodology to debug LVS/DRC issues at both device, block and top levels.

Preferred Qualifications:

• Firm grasp of programming tools and knowledge in VLSI domain
• Excellent working ability with circuit design and layout methodologies in a team environment.
• Capable of sharing tool knowledge and expertise with other physical designers and contribute to a positive team environment through developing and proliferating best known methods

Intel Labs is the company's world-class, industry leading research organization, responsible for driving Intel's technology pipeline and creating new opportunities. The mission of Intel Labs is to deliver breakthrough technologies to fuel Intel's growth. This includes identifying and exploring compelling new technologies and high risk opportunities ahead of business unit investment and demonstrating first-to-market technologies and innovative new usages for computing technology. Intel Labs engages the leading thinkers in academia and industry in addition to partnering closely with Intel business units.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.