Come join Intel's Client Engineering Group responsible for designing Client SoCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of laptops and desktop computers.

The DDG (Device Development Group) SOC design team is looking for an IP handoff qualification engineer who will enjoy engaging in the full spectrum of IP and SOC design development and is interested in having exposure to the entire lifecycle of SOC projects, while taking a fast-paced, empowered, hands-on engineering approach.

As part of our team, you will work with IP providers and SOC customers to review and certify IP quality that prevent downstream escapes to SOC customers. In this role, you will be responsible for ensuring a high-level IP quality for delivery to SOC involving both Intel and external IP providers. This responsibility includes understanding program and process technology requirements for IP delivery for both back end and front end domains. It also requires enforcing quality checking rules and debugging misalignments between spec and IP delivery. An ideal candidate will identify gaps in tools, flows, and methodologies and drive enhancements through various Intel wide work group engagement to improve quality within the IP, the SOC, and Intel.

Other essential aspects of this role include:

• Coordinating interactions between IP providers, the IP office team, and the various SOC design domain owners.

• Interest and proficiency in scripting to automate and innovate for productivity improvement and enhanced capabilities is also valued.

• Willing to understand what it takes to root cause issues by learning and understanding IP standardizations, level of quality per a given milestone, understanding IP handoff tools (Ship, Riptide, Crossfire, etc.). The candidate should have solid debugging skills and eye for finding potential issues.

• Technical understanding of SOC or IP design development across front end and back end domains, tools/methods, or have a keen interest in growing knowledge in all such domains.

• The ideal candidate will possess a Si design background and be interested in leveraging that technical experience to ensure smooth high quality IP delivery for SOC integration and design convergence.

The candidate should also be strong in the behavioral skillset needed to tackle the breadth of challenges that arise when operating with broad scope, high complexity, and large stakeholder networks such as:

• Excellent written, verbal, and presentation communication skills with an willingness to articulate technical problems, solutions, and issues as they arise.

• Attention to detail with solid problem solving and organizational skills to manage multiple complex tasks, define and leverage indicator data, and proactively drive issue closure at a technical level.

• Motivation to take on new tasks which require continuous technical and organizational learning and to find ways to improve pain points and innovate work-models for greater productivity.

• Willing to work with a variety of teams across GEOs and desire to influence for results.

• The role has potential to expand into technical program management as skills grow in the IP handoff domain.

• The candidate may assist more senior program managers as they negotiate commitments, align requirements, define methodology, verify quality, and manage performance to schedule.

Qualifications

You must possess the below qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• BS or MS in Computer Science, Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering.

• 2+ years of experience in silicon development.

• 2+ years of experience in SOC or IP development.

Preferred Qualifications:

• Familiarity with Intel SOC/IP ecosystem tools and process including Carbon, HSD, PLC, IP Handoff flows and SIP/HIP handoff/integ standards.

• Knowledge in multiple SOC and IP design domains including Timing, Layout, Low Power (mpp/upf), DFx, Analog, Memory and associated design/verification/quality flows.

• Proficiency with scripting in Unix Env using Python/Perl/Shell.

• Previous experience and/or desire to grow program management skills.

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.