5 days old

SOC Design Engineer

Phoenix, AZ 85003
  • Job Code
Job Description
The world is transforming - and so is Intel! Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world.With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver IP solutions for products that impact customers lives? If so, Come join us to do something wonderful!The Mixed signal IP development group at Intel develops cutting edge High Speed IO designs like PCIE Gen6, USB and Type C Phys for use in Intel's latest microprocessors. We own the design from architecture definition to tape-out and Post Silicon support covering all aspects of a Mixed Signal design from Analog circuit to RTL development and structural implementation.Responsibilities will include but not limited to:Front end design of several logic blocks dealing with clock and data recover of a serial IO, Power Management, Protocol compliance and logic behaviors of a High Speed Serial IO.You will be responsible for Micro Architect, Develop Specification and Perform detailed logic design at the block level.You will perform block level verification and collaborate with Verification team to validate the design.You will also support the DFT implementation and timing closure.As a mixed signal team expect to interact/help with behavioral modelling of custom building blocks.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:Candidate will have a Bachelor's degree with Electrical, Computer Engineering and 6+ years of experience -OR- a Master's degree in Electrical, Computer Engineering with 4+ years of experience in:RTL design and verification experience of high performance low power designs.Understanding of methodologies for physical design and SOC and/or IP designsDeveloping timing constraints, working knowledge of Prime Time, Timing ClosureWorking knowledge of Floor planning, CTS and routing in the Auto Place and route (APR) domainsSoC Tools and flows methodologies (TFM) (including Power Domains, UPF etc)Preferred Qualifications: Experience in:ASIC-based designsImplementing new flows based on industry-standard toolsPhysical design convergenceIndustry-standard RTL toolsHigh Speed IO, DMA, AMBA and IOSF bus protocolTape in, tape out

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Folsom;US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-23 Expires: 2022-06-24

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SOC Design Engineer

Phoenix, AZ 85003

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