Join Intel and build a better tomorrow. At Intel you can help build computing technology to connect and enrich the lives of every person on Earth.

As part of Advanced Design (AD) within Design Enablement (DE) organization, this team works on Design and Technology Co-Optimization (DTCO) in close collaboration with various partners from technology development to design teams spanning Client, Graphics, Networking, Servers, and FPGA. The primary focus of the team is to accurately predict power, performance, and area (PPA) impact from various process technologies to facilitate quick data-driven decision making for partners and customers.

You will enjoy:

• Solving unique problems and challenges
• Being self-driven and resourceful in a fast-paced team environment
• Exploring new techniques for design optimization (including but not limited to AI/ML)
• Learning about new process technologies

About the role:
You will work as part of a team supporting RTL synthesis, place and route (PnR), timing and power analyzes using internal and external EDA tools to optimize PPA for products on Intel Architecture (IA/X86) and external IP's using various advanced process technologies. You are expected to optimize floorplan and PnR for low-power, routing congestion, and timing closure as partition owner. Understand PPA trade-off to predict technology scaling on power and performance for future technology nodes. Drive to improve cell utilization and transistor density by leveraging leading edge tools and methodologies in close collaboration with EDA vendors.

This is an entry level position and compensation will be given accordingly.

Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:
Master's degree in Electrical or Computer Engineering + 6+ months experience in the following areas:

• ASIC design flow including: floor planning, clock methodologies, EM/IR and SI mitigation strategies, power and timing sign-offs
• At least one of the following scripting languages: Python, TCL, and Shell

Preferred Qualifications:

• Industry experience of low-power and high-performance optimizations, and PPA tradeoffs
• Experience in graphic designs and architectures
• Knowledge in Artificial Intelligence and Machine Learning (AI/ML)

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.