3 days old

SoC Design Engineer

San Jose, CA 95113
  • Job Code
Job Description

The Programmable Solutions Group (PSG) will continue to drive the future for FPGAs and Structured ASICs to build a better tomorrow. By pushing forward in cutting edge technology our work is at the heart of innovation. With a career at Intel you have the opportunity to shape the future for everyone.

As a SoC Full Chip Design Engineer, you will be developing timing and power methodologies and executing full-chip timing for Intel's Programmable Solutions Group's next generation product lines in the world's most advanced process technologies. This will be a fast-paced dynamic environment where you will be part of a high-performance design team working toward next generation FPGA products. You will work in a hands-on capacity performing full chip timing and power analysis. You will utilize your extensive design experience and interpersonal skills to efficiently solve technical issues, drive continuous improvement, negotiate and clearly communicate technical tradeoffs with a diverse cross-functional and multi-site team. You must be capable to work to aggressive schedules as part of a team and also independently.

In this role, you will (will bring):
Design and Architecture understanding, Interaction with FE and BE teams, Clocking, Constraints development, understanding extraction issues, design margins, timing signoff and quality checks. collaborate with cross-functional teams to define system level power optimization solutions, provide power targets to design teams, and commit product power to meet business goals. You will also be part of debug and troubleshooting for a wide variety of tasks up to and including difficult, critical design issues and proactive intervention.


Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications

4+ years of relevant experience, experience should include:

  • Experience in SoC/Digital Design.

  • Experience of power analysis (e.g. model generation, low power strategy, power analysis tools such as Primetime-PX, Redhawk, Power Artist and/or Spice).

  • Experience with Timing Analysis (e.g. STA, Spice, ASIC timing formats such as Liberty, SPEF, Verilog, and SDC).

  • Experience in flow or tool development using Python, Perl, and/or TCL.

Preferred Qualifications

Experience in one or more of the following is considered a plus factor

  • 8+ years of relevant experience in power and timing domains.

  • Experience in the following protocols or domains: DDR, PCIe, Ethernet, HBM, and/or FPGA.

  • MS in Electrical Engineering, Computer Engineering, or related fields.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, Santa Clara;US, Oregon, Hillsboro;US, Texas, Austin

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Posted: 2022-05-22 Expires: 2022-06-22

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SoC Design Engineer

San Jose, CA 95113

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