In this position you will be part of the world class SOC design team within the Xeon Performance Group XPG designing the next generation Xeon SoCs/IPs for Server markets.

Your responsibilities will include but not be limited to:

• Full Chip high speed fabrics design
• Full chip DFT and DFD fabrics design
• Full Chip and subfc level Timing model builds/analysis
• Fullchip clocks and timing constraints generation/verification
• Fullchip timing quality convergence and Full Chip Timing convergence using Synopsys Fusion/ICC tools
• Timing verification using Synopsys PrimeTime as well as Fishtail and simulations using Synopsys/Intel tools

Behavioral Traits

• Excellent analytical and independent/creative problem-solving skills
• Excellent communication and leadership skills to work through several teams across multiple geographies

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Candidate must have a Bachelor's degree in Electrical/Computer Engineering, Computer Science or closely related technical field and 8+ years of experience in/with: - OR - a Masters degree in Electrical/Computer Engineering, Computer Science or closely related technical field and 5+ years of experience in/with: - OR - a PhD in Electrical/Computer Engineering, Computer Science or closely related technical field and 2+ years of experience in/with:

• Semiconductor fundamental's and device physics
• Circuit design
• Modern SOC design
• Primetime OR PTECO/PrimeECO OR equivalent timing convergence tools OR Circuit/IP/SOC timing

Preferred Qualifications

Experience with/in:

• Converging Fullchip level or IP level timing
• Post silicon debug, speed push, vmin characterization and post silicon design fix
• Circuit design and end to end RTL2GDS design convergence
• ICCDP and Formal Equivalence
• TCL, Perl, Python programming
• Timing convergence in multiple internal and external to Intel process technologies
• Timing convergence with Cadence timing verification tools

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.