6 days old

SOC Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0219111
Job Description

Intel's Xeon Server Development Group is looking for a highly motivated logic designer to join a seasoned team as a key team member designing future generation Intel Xeon SoCs and associated IPs.

What we offer:

  • We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.  

  • As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results.  

  • We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).  

  • We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and much more creative perks that make Intel a Great Place to Work!  

  • We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow.


Your responsibilities will include but not be limited to:

  • Working with architects to understand design requirements.

  • Write detailed micro-architectural specifications for design blocks capturing functional blocks to be coded and existing IP to be integrated.

  • Perform RTL coding that meets functional, area, power and timing goals.

  • Ensure design passes Quality Checks including Lint, CDC, Low Power Checks etc.

  • Work closely with verification team to bring-up and debug design in simulations.

  • Work closely with physical design team to ensure design is physically implementable.


The ideal candidate should exhibit the following behavioral traits:

  • Solid problem-solving skills and willingness to multitask.

  • Excellent written and verbal communication skills.

  • Willing to work in a dynamic and team-oriented environment.

  • Excellent collaboration skills.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.  

Minimum Qualification:

  • Must have a Bachelor's degree in Electrical/Computer Engineering, Computer Science or related field with 6+ years of relevant experience.

OR

  • Master's degree in Electrical/Computer Engineering, Computer Science or related field with 5+ years of relevant experience.


Your experience will be in the following:

  • System Verilog for RTL design of IP and Subsystems.

  • Integrating complex IP (Examples: CPU Cores, Memory Controllers, IO devices, Fabrics) into large SoCs.

  • Exposure/knowledge of SoC/ASIC/IP design methodology.


Preferred Qualifications:

  • Experience with interconnect fabric IP development.

  • Experience with SoC flows for Reset, Power Management, Interrupts and Error Handling.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.



Other Locations

US, California, Folsom;US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-06-28 Expires: 2022-07-29

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SOC Design Engineer

Intel
Santa Clara, CA 95050

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