6 days old

SoC Design Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

The world is transforming and so is Intel!  Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful!

The XSD (Xeon Silicon Development) Group is looking for a highly motivated Design Engineer to join the Compute-Die Front-End Design Team for the next generation of Xeon processor. The role involves Logic Design as well as a good amount of focus on Validating of High-Speed Memory functionality and Design-for-Debug functionality, the latter used for post-Silicon debug in the Power-On phase of the projects.

Your responsibilities will include but not limited to:

  • Leading Design and Validation efforts including automation and scripting
  • Debugging design environment issues including follow up with cross-functional teams as needed
  • Repository, revision, and release management
  • Working with cross-functional teams to ensure Validation key metrics are delivered on time, with high quality, by incorporating proper checks at every stage of the Validation process

In addition to the qualifications listed below the ideal candidate will also have:

  • Excellent analytical and problem-solving skills
  • Strong verbal/written communication skills
  • Effective team player with continuous learning mindset
  • Willingness to balance multiple tasks
  • Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 6+ years of experience - OR - Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4+ years of experience with:

  • Design and Validation fundamentals
  • RTL Design and understanding of resulting Gate level implementation including Timing as well as Validation metrics and concepts such as code coverage, functional coverage, Score Board/checker, assertions, regression suites etc.
  • Programming and scripting skills in general and SystemVerilog and UVM/OVM specifically
  • Ability to work independently and proactively Lead Technical activities

Preferred Qualifications: experience with

  • Git, Perforce or similar tools
  • Formal Verification (functional and/or equivalence checking)
  • Xeon server and SoC design

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-06-28 Expires: 2022-07-29

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SoC Design Engineer

Santa Clara, CA 95050

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