2 days old

SOC Design Engineer - Senior IP Office Program Manager

Hillsboro, OR 97123
  • Job Code
Job Description

Come join Intel's Design Engineering Group, responsible for designing Client SoCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of laptops and desktop computers.

We are looking for an SoC (System on Chip) Senior Technical Program Manager, who will enjoy engaging in the full spectrum of IP and SOC design development. This role is for someone interested in having exposure to the entire lifecycle of SOC projects while taking a fast-paced, empowered, hands-on engineering approach. It is within Intel's highly regarded Devices Development Group headquartered in Portland, Oregon with additional sites in Austin, Texas and Penang, Malaysia. Our bold purpose as a company is to 'create world changing technology that enriches the lives of every person on earth', and this role is instrumental in furthering our mission to shape the future of technology.

In this role, you will be responsible for driving forward progress on all IP coordination related fronts involving both Intel and external IP providers. It includes alignment of IP and SOC expectations and requirements, managing scope, ensuring accountability to schedule, verifying quality of IP deliverables, identifying and resolving technical problems, and managing interdependencies across a wide-variety of IPs and stakeholders involving several design domains from FE to BE development. As part of our team, you will contribute during early project definition/scoping phases, own project execution as it relates to IP delivery to the SOC, and participate in postSi stepping support.

Other essential aspects of this role include:

  • Coordinating interactions between IP providers and the various SOC design domains by leveraging cross-org forums and collaboration WGs, dedicated focus topic mtgs, and direct DE/PM engagement.
  • Synthesizing, abstracting, and representing complex information into clear, refined messages, and negotiating, tracking, and proactively driving complex issues to aligned PORs.
  • Leveraging relationships and expertise while exercising judgment and discretion to develop optimized and aligned solutions, remove obstacles, and drive execution. As part of this process, the candidate will be required to assess risks and help identify technical and non-technical solutions to efficiently and effectively achieve program goals, ensure quality standards and design constraints are met, and track appropriate progress against schedule taking mitigating action as appropriate.

The ideal candidate will have:

  • Technical understanding of SOC or IP design development across architecture, logic, validation, physical implementation/convergence, tools/methods, or a keen interest in growing knowledge in all such domains.
  • A silicon design background and interest in leveraging that technical experience to ensure smooth and high-quality IP delivery for SOC integration and design convergence.

The candidate should also be strong in the behavioral skill set needed to tackle the breadth of challenges that arise when operating with broad scope, high complexity, and large stakeholder networks, including:

  • Strong written, verbal, and presentation communication skills, with an ability to create concise summaries of plans, status, and risk/issue mitigation.
  • Attention to detail with strong problem-solving and organizational skills to manage multiple complex tasks, define and leverage indicator data, and proactively drive issue closure at a technical level.
  • Ability to influence others, and to build and manage effective stakeholder relationships both internal to the SOC team and with partner organizations such as IP, Arch, and PostSi teams.
  • Motivation to take on new tasks which require continuous technical and organizational learning and to find ways to improve pain points, and innovate work models for greater productivity.
  • Interest in directly managing a small team of ICs is also a plus.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education Requirement
Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering.

Minimum Qualifications
8+ years of experience in silicon development.
4+ years of experience in SOC chip or IP development.

Preferred Qualifications
2 years or more of experience in managing or leading technical teams as a technical FLM, Program manager, or Tech lead type role.
Familiarity with Intel SOC/IP ecosystem tools and processes including Carbon, HSD, PLC, IP Handoff flows and SIP/HIP handoff/integ standards.
Knowledge in multiple SOC and IP design domains including Timing, Layout, Low Power (mpp/upf), DFx, Analog, Memory and associated design/verification/quality flows, as well as experience with the Industry vendor IP ecosystem.
Proficiency with scripting in the Unix environment using Python, Perl, or Shell.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Posted: 2022-05-19 Expires: 2022-06-19

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SOC Design Engineer - Senior IP Office Program Manager

Hillsboro, OR 97123

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