13 days old

SOC Design Engineer - SOC DFT Integration

Intel
Hudson, MA 01749
  • Job Code
    JR0216807
Job Description

In this role you will be part for the Scalable Performance CPU Development Group (SDG) design team, working on next-generation Xeon server product SOCs and IPs.

  • Work as a part of the SOC integration team.

  • Own both DFT tile integration as well as global fabric distribution.

  • Analyzes and uses results to drive bug fixes into both SOC RTL as well as tiles.

  • Own DFT tile integration; work collaboratively with multiple IP teams to ensure correctness.

  • Own global fabrics integration: work collaboratively with physical design team as well as architecture team to ensure architectural correctness of the implementation as well as satisfying physical requirements.

  • Work in close collaboration with full chip validation team to assist in debug .

Job responsibilities for this role include but are not limited to:

  • Be responsible for the RTL integration of one or more IPs/tiles into the server SoCs, starting with Tech Readiness through RTL1.0 and Tape-In. Technology Readiness (TR) work will include assessing new IPs/features, TFM proposed changes design effort/complexity, etc.

  • Ensure that the incoming SIPs/HIPs you are responsible for meet the quality expectations for each SoC milestone and meet SoC design schedules.

  • Work closely with the SoC Verification and Emulation teams to debug failures, with the SoC Structural Design team on timing constraints and exceptions, etc.

  • In addition, you will collaborate with the SIP/HIP teams, track IP bugs, scope and define netlist ECOs, identify bug workarounds, assess the impact of bugs and make recommendations on bug fixes.

  • You will also be responsible for milestone and paranoia checklist reviews and post-Silicon debug support.

In addition to the qualifications listed below, the ideal candidate will also have:

  • Willingness to multitask.

  • Good interpersonal skills.

  • Willingness to work in a highly cooperative team environment across several time zones.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Candidate must have earned a Bachelors Degree in Electrical Engineering, Computer Engineering, or Computer Science and have 3+ years of Industry experience .

OR

  • Masters Degree in Electrical Engineering ,Computer Engineering, or Computer Science and have 2+ years of Industry experience.


Qualifying industry experience includes:

  • Experience with IC/SoC Design or integrating internal/3rd party IPs into SoC products.

  • Experience in all phases of logic development lifecycle from high-level specification to tape-out and production.

  • Experience using Synopsys Coretools or VCS/Modelsim or Synopsys Design Compiler or Spyglass or Lint.

  • Experience using following languages like Verilog or System Verilog or Perl or Tcl or Python or C/C++.


Preferred Qualifications:

  • Experience with Unified Power Format (UPF) methodology (implementation and simulation).

  • Experience with OVM/UVM.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.



Other Locations

US, California, Santa Clara


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role is available as fully home-based and generally would require you to attend Intel sites only occasionally based on business need.

Posted: 2022-05-14 Expires: 2022-06-14

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SOC Design Engineer - SOC DFT Integration

Intel
Hudson, MA 01749

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