In this role you will be part for the Scalable Performance CPU Development Group (SDG) design team, working on next-generation Xeon server product SOCs and IPs.  

Responsibilities include but are not limited to:

• RTL integration of one or more IPs/tiles into the server SoCs, starting with Tech Readiness through RTL1.0 and Tape-In.
• Technology Readiness (TR) work will include assessing new IPs/features, TFM proposed changes design effort/complexity, etc.
• Ensure that the incoming SIPs/HIPs you are responsible for meet the quality expectations for each SoC milestone and meet SoC design schedules
• Work closely with the SoC Verification and Emulation teams to debug failures, with the SoC Structural Design team on timing constraints and exceptions, etc.
• Collaborate with the SIP/HIP teams, track IP bugs, scope and define netlist ECOs, identify bug workarounds, assess the impact of bugs and make recommendations on bug fixes
• You will also be responsible for milestone and paranoia checklist reviews and post-Silicon debug support 

Traits:

• Excellent multi-tasking skills
• Interpersonal skills
• Willingness to work in a highly cooperative team environment across several time zones

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must have earned a Bachelors Degree in Electrical Engineering or Computer Engineering or Computer Science and have 3+ years of industry experience or must have earned a Masters Degree in Electrical Engineering or Computer Engineering or Computer Science and have 2+ years of industry experience.

Qualifying industry experience includes:

• Experience with IC/SoC Design or integrating internal/3rd party IPs into SoC products
• Experience in all phases of logic development lifecycle from high-level specification to tape-out and production
• Experience using Synopsys Coretools or VCS/Modelsim or Synopsys Design Compiler or Spyglass or Lint
• Experience using following languages like Verilog or System Verilog or Perl or Tcl or Python or C/C++

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.