7 days old

SoC DFT Design Engineer

Fort Collins, CO 80524
  • Job Code
Job Description

Seeking candidates for Design for Test (DFT) Engineering role at an SoC Organization. The successful candidate will be contributing to achieving high DFT coverage across IPs and SoCs to achieve low DPM through quality ATPG content generation and being able to quickly contribute to DFT network integration in large, complex IPs or SOCs and be able to verify the same. The role is within a SoC organization, comprising varied IP, with both front end and back end opportunities in varied designs, across geographical boundaries.

In this role responsibilities include, although not limited to:

  • Understand scan architecture of complex designs; DFT architectures and their relationships with clocks, resets, debug, and power.

  • Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan DRC tools.

  • Integration and verification of DFT fabrics and IP within Subsystems.

  • Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage.

  • Run ATPG analysis to ensure quality scan chain construction and meeting basic coverage goals.

  • Creating ATPG content for use in post-Si testing and validating that content through gate level simulation.

  • Array Test implementation and verification.

  • Must collaborate with circuit physical design team, ATPG team, and manufacturing team to facilitate high quality scan coverage in silicon.

  • Work with the tool methodology teams on defining and regressing the tool flows.

In addition to the qualifications listed below, the ideal candidate will also have:

  • Ideal candidate is a self-starter, willing to organize complex issues and drive them to closure.

  • Candidate can multitask and prioritize.

  • Candidate is willing to mentor and lead junior engineers.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must possess a bachelors in electrical or Computer Engineering or relevant field with 4+ years of experience


Masters degree in electrical or Computer Engineering or relevant field with 2+ years experience


PhD in electrical or Computer Engineering or relevant field with 6 months experience.

Preferred Qualification:

  • DFT integration and validation; RTL experience to understand, trace, and debug RTL connectivity issues as they pertain to DFT.

  • Scan insertion; preferably using DFT-Compiler and Synopsys synthesis tool suites. Git repositories and front-end regressions.

  • ATPG tools, preferably Mentor TestKompress.

  • SpyGlass DFT experience in setup and debug of violations.

  • UPF, formal verification and DRC rule checking experience required.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

Virtual US and Canada

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Intel is committed to a culture of accessibility.  Intel provides accommodations to applicants and employees with disabilities.  Find information and request accommodation here

Posted: 2022-05-16 Expires: 2022-06-17

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

SoC DFT Design Engineer

Fort Collins, CO 80524

Join us to start saving your Favorite Jobs!

Sign In Create Account
Powered ByCareerCast