4 days old

SOC DFX Validation Component Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

Come join the exciting Xeon Engineering Group (XEG) as a SOC DFX Validation engineer. In this role you will be responsible for DFX Validation ranging from validation infrastructure planning, validation collaterals development, testplan writing, and test content development and debug in the SOC.

Your responsibilities may also include:

  • Working closely with architects and other design engineers to develop verification infrastructure and test plan of the relevant IP, Subsystem, or SOC.

  • Be familiar with design and verification environment, flow, tools, and methodologies.

  • Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs.

  • Written/verbal communication skills and strong team work.

  • Self-motivated and able to work effectively both independently and in a team.

You must have working knowledge of DFT or DFD architectures and techniques which include familiarization of debug fabric, probe-less debug and test methodology, scan, JTAG standards, Bscan, memory BIST, IODFT, and/or Burn-in. You must have hands-on experience of DFT or DFD Validation. You should have high competency in System Verilog coding, OVM/UVM, VCS simulation, Emulation, and debug.

The ideal candidate should exhibit the following behavioral traits:

  • Problem-solving skills.

  • Willing to multitask.

  • Solid written and verbal communication skills.

  • Willing to work in a dynamic and team oriented environment.

  • Willing to flex between multiple roles throughout the progress of the project and continuously upgrading your skills.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

  • BS in Electrical Engineering or Computer Engineering with 5+ years of experience with design or validation and at least 2 years of DFT/DFD validation experience.

  • MS in Electrical Engineering or Computer Engineering with 4+ years of experience with design or validation and at least 2 years of DFT/DFD validation experience.

Preferred Qualifications:

  • Post-silicon platform or system debug, high volume manufacturing (HVM) experience, hands-on knowledge of high-speed testers (ATE).

  • Experience with emulators.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-21 Expires: 2022-06-21

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SOC DFX Validation Component Engineer

Santa Clara, CA 95050

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