22 days old

SoC IP Modeling Engineer

Hillsboro, OR 97123
  • Job Code
Job Description

About the role:
You will participate in qualifying modeling and simulation accuracy of digital, analog and mixed-signal foundational IPs being designed by our Advanced Design (AD) team and thereby contributing to the quality of our process design kits (PDKs). You will be responsible for analyzing the power, performance and area (PPA) impact from ongoing process file changes on a given technology node, thereby contributing to establishing PPA targets at the IP level.

Your responsibilities will include, but may not be limited to:

  • Tracking ongoing changes in transistor and interconnect models for every revision of a PDK, in addition to assessing their impact on PPA.
  • Running field solver simulations to serve as a reference for qualifying extraction modeling accuracy.
  • Qualifying and validating post-layout extraction modeling and simulation accuracy.
  • Familiarizing oneself with the interaction between process collateral and extraction tool flow and methodology variants.
  • Formulating specification for extraction QA automation infrastructure to enable running regressions that track changes in process collateral, and extraction tool flows and methodologies.

Important behavioral traits we look for:

  • Customer oriented mindset
  • Ability to work with multiple external and internal partners

About the team:

  • This position is with the Library Technology Benchmarking team within the Logic Technology Development's (LTD) Advanced Design (AD) Organization.
  • This group works closely with both process and product design teams, to deliver capabilities that optimize and integrate Foundational IP standard logic cells, memory cells and analog templates designed using Intel's leading-edge process technology.



You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:
A Master's degree in Electrical Engineering, Computer Engineering or Electrical and Computer Engineering, and 3 or more months of internship or professional work experience in following areas:

  • Design of digital, analog or mixed-signal circuits in CMOS
  • EDA tools used in one or more of the following areas: circuit simulation and modeling, physical design, or post-layout design validation.
  • Coding experience using one or more the following languages for design automation: C/C++, Python, Tcl or Perl.

Preferred Qualifications:

  • Field Solver simulations

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-04 Expires: 2022-06-04

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SoC IP Modeling Engineer

Hillsboro, OR 97123

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