11 days old

SoC Layout Methodology Engineer

Hillsboro, OR 97123
  • Job Code
Job Description

We are looking for an SoC Design Engineer to work on Test Chip Lead Vehicles, which are primarily used by our Design Enablement (DE) and Logic Technology Development (LTD) team for Intel's next generation technology development and high-volume certifications.

This role primarily focuses on the physical design domain and includes engagement with manufacturing partners on cutting-edge process nodes.

This role includes, but is not limited to, the following responsibilities:

  • Developing layout design methodology and productivity automation for cutting edge process nodes
  • Building and executing tactical plans to converge hierarchical SoC layout designs against aggressive schedule requirements
  • Qualification of the fullchip design to meet tape-out requirements
  • Working with tool/flow owners and vendors for ongoing tool/methodology improvement
  • Motivation to continuously learn and drive to push improved layout productivity and efficiency


Minimum Qualifications:

  • Master's degree in Electrical Engineering or Computer Engineering
  • 6+ months of academic or professional experience in the following areas: Experience with layout and layout tools; Design rule checking (DRC) and Layout vs Schematic (LVS)

Preferred Qualifications:

  • Familiarity with Cadence Virtuoso, Synopsys ICC2, ICC2-DP, Synopsys ICV or Calibre rule decks
  • Familiarity with scripting or programming languages, such Perl, Python, TCL etc.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Other Locations

US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-08-03 Expires: 2022-09-03

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SoC Layout Methodology Engineer

Hillsboro, OR 97123

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