28 days old

SOC Physical Design and STA Lead

Santa Clara, CA 95050
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Job Description

Custom logic ASIC engineering organization (Part of Datacentric and Artificial Intelligence group) is seeking an industry-experienced leader to join our custom silicon design team as a System On Chip (SOC) Physical design and Static timing analysis (STA) lead. The Custom ASIC business is poised for explosive growth in areas such as custom processors, accelerators for Application processing (AI and media) and Infrastructure (Smart NIC and switches), and this is your chance to help define and drive our success.

As a SOC physical design and STA lead, you will be an integral member of a small team developing and executing the design of leading-edge custom products for large data center customers.

Responsibilities include but are not limited to:

  • Work with the team to develop, plan and track pre-silicon timing verification for various sub-system timing verification tasks.
  • Provide leadership and develop state of the art full chip timing verification techniques utilizing POCV, spatial variation, interconnect variation on latest process nodes like TSMC 7nm, TSMC 5nm, Intel 7, Intel 3, etc. (spanning both Intel foundry as well as TSMC)
  • Lead development of full chip timing constraints including knowledge of DFT timing constraints and DFT mode timing validation in STA.
  • Work closely with ASIC design implementation (including physical design execution as needed , global clocking and development/execution per low power design techniques.
  • Work closely with Customer to support full chip integration activities.
  • Drive and provide supervision/liaison with 3rd party IP/sub-system suppliers to ensure timing spec compliance, understanding clocking interaction between IP and SOC and high-quality end-customer deliverables.

The ideal candidate should exhibit the following behavioral traits:

  • Managing timing risks in the program and plans to triage timing paths to ensure on time tapeout.
  • Complex problem solving and decision making with a proven record of results orientation.
  • Skills to work effectively with global teams in a variety of geographies.
  • Excellent communication skills, proficient to synthesize complex info into easy to digest form for senior management.


Education Requirement

  • Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field with 6+ years of industry work experience, or
  • Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field with 4+ years of industry work experience, or
  • PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field with 2+ years of related work experience.

Minimum Qualifications

  • Experience with Synthesis, APR, STA / full chip timing of high performance silicon products for data center products (example with Serdes/MAC sub-systems ), high performance designs.
  • Experience creating and maintaining chip-level timing indicators.
  • Experience with tools / Languages: Fusion compiler, Primetime, Fishtail, Verilog, Tempus, Perl/Python (or similar tools from other vendors).

Preferred Qualifications

  • Experience in physical design / STA of complex SOC/ASIC development programs.
  • Experience with uncompromising customer orientation to deliver leading-edge silicon products.
  • Experience in verifying high-speed timing interfaces like DDR/HBM/PCI-Express/Serdes/Ethernet MAC with SOC Core clock.
  • Experience with verification of system level power up/reset sequence/power management for complex SOC's and understanding its implications on STA (like low power STA with UPF techniques).
  • Post-silicon validation skills.

Inside this Business Group

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, Arizona, Phoenix;US, Oregon, Hillsboro;US, Texas, Austin

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Jobs Rated Reports for Physicist

Posted: 2022-06-03 Expires: 2022-07-04

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SOC Physical Design and STA Lead

Santa Clara, CA 95050

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19th2019 - Physicist
Overall Rating: 19/199
Median Salary: $117,220

Work Environment
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