About the role:
Perform all aspects of the SoC design flow from synthesis on sign-off, including Clock-Tree Synthesis (CTS), Static Timing Analysis (STA) and Place and Route (PNR) optimization. You will leverage leading edge tools and design methodologies to achieve best-in-class PPA for Intel's process technologies.
 

To excel in this role, you should be passionate about physical design, solving challenging problems, and exploring cutting-edge technologies for design optimization including the use pf AI/ML techniques.

You'll be part of Advanced Design (AD) within Design Enablement organization (DE). The team works in close collaboration with various partners in process technology and design teams spanning CPU, GPU and Server SoCs. The primary focus of the team is to accurately predict the impact of process changes on power, performance, and area (PPA) to facilitate data-based decisions for PPA commits for future Intel processes.
 

Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:
Bachelor's degree in Electrical or Computer Engineering with 2 or more years of academic or professional experience OR a master's degree in the same disciplines listed above.

Experience must be in the following areas:

• Fundamentals in block-level digital circuit design.
• One or more of the following scripting languages: Python, Perl, Tcl or Shell.
• EDA tools from Cadence and Synopsys for Place and Route (PNR)

Preferred skills:

• Floor planning, power grid setup, clock methodologies, IR droop and SI mitigation strategies.
• Power and timing optimization techniques that leverage industry standard tool flows and methodologies for the best possible PPA.
• Experience performing feasibility or technology pathfinding
• Expertise in Artificial Intelligence and Machine Learning (AI-ML) for design optimization.
   

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.